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/linux-6.3-rc2/drivers/gpu/drm/etnaviv/
A Detnaviv_gpu.c403 gpu->identity.model, gpu->identity.revision); in etnaviv_hw_identify()
485 gpu->base_rate_core >> gpu->freq_scale); in etnaviv_gpu_update_clock()
1064 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_gpu_recover_hang() local
1164 f->gpu = gpu; in etnaviv_gpu_fence_alloc()
1369 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_gpu_submit() local
1451 event_free(gpu, gpu->sync_point_event); in sync_point_worker()
1537 queue_work(gpu->wq, &gpu->sync_point_work); in irq_handler()
1633 if (gpu->initialized && gpu->fe_running) { in etnaviv_gpu_hw_suspend()
1752 priv->gpu[priv->num_gpus++] = gpu; in etnaviv_gpu_bind()
1845 dev_name(gpu->dev), gpu); in etnaviv_gpu_platform_probe()
[all …]
A Detnaviv_sched.c37 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_sched_timedout_job() local
58 if (gpu->completed_fence != gpu->hangcheck_fence || in etnaviv_sched_timedout_job()
60 gpu->hangcheck_dma_addr = dma_addr; in etnaviv_sched_timedout_job()
61 gpu->hangcheck_fence = gpu->completed_fence; in etnaviv_sched_timedout_job()
74 drm_sched_start(&gpu->sched, true); in etnaviv_sched_timedout_job()
79 drm_sched_start(&gpu->sched, true); in etnaviv_sched_timedout_job()
100 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_sched_push_job() local
108 mutex_lock(&gpu->sched_lock); in etnaviv_sched_push_job()
127 mutex_unlock(&gpu->sched_lock); in etnaviv_sched_push_job()
139 dev_name(gpu->dev), gpu->dev); in etnaviv_sched_init()
[all …]
A Detnaviv_buffer.c94 lockdep_assert_held(&gpu->lock); in etnaviv_cmd_select_pipe()
102 if (gpu->exec_state == ETNA_PIPE_2D) in etnaviv_cmd_select_pipe()
166 lockdep_assert_held(&gpu->lock); in etnaviv_buffer_init()
183 lockdep_assert_held(&gpu->lock); in etnaviv_buffer_config_mmuv2()
218 lockdep_assert_held(&gpu->lock); in etnaviv_buffer_config_pta()
240 lockdep_assert_held(&gpu->lock); in etnaviv_buffer_end()
242 if (gpu->exec_state == ETNA_PIPE_2D) in etnaviv_buffer_end()
306 lockdep_assert_held(&gpu->lock); in etnaviv_sync_point_queue()
354 lockdep_assert_held(&gpu->lock); in etnaviv_buffer_queue()
437 gpu->flush_seq = new_flush_seq; in etnaviv_buffer_queue()
[all …]
A Detnaviv_gpu.h159 writel(data, gpu->mmio + reg); in gpu_write()
164 return readl(gpu->mmio + reg); in gpu_read()
170 if (gpu->identity.model == chipModel_GC300 && in gpu_fix_power_address()
171 gpu->identity.revision < 0x2000) in gpu_fix_power_address()
179 writel(data, gpu->mmio + gpu_fix_power_address(gpu, reg)); in gpu_write_power()
184 return readl(gpu->mmio + gpu_fix_power_address(gpu, reg)); in gpu_read_power()
189 int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
197 void etnaviv_gpu_retire(struct etnaviv_gpu *gpu);
200 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
204 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu);
[all …]
A Detnaviv_perfmon.c18 u32 (*sample)(struct etnaviv_gpu *gpu,
66 pipe_select(gpu, clock, i); in pipe_perf_reg_read()
71 pipe_select(gpu, clock, 0); in pipe_perf_reg_read()
85 pipe_select(gpu, clock, i); in pipe_reg_read()
86 value += gpu_read(gpu, signal->data); in pipe_reg_read()
90 pipe_select(gpu, clock, 0); in pipe_reg_read()
106 return gpu_read(gpu, reg); in hi_total_cycle_read()
120 return gpu_read(gpu, reg); in hi_total_idle_cycle_read()
508 dom = pm_domain(gpu, domain->iter); in etnaviv_pm_query_dom()
533 dom = pm_domain(gpu, signal->domain); in etnaviv_pm_query_sig()
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A Detnaviv_drv.c73 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_open() local
76 if (gpu) { in etnaviv_open()
100 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_postclose() local
102 if (gpu) in etnaviv_postclose()
222 gpu = priv->gpu[i]; in show_each_gpu()
264 gpu = priv->gpu[args->pipe]; in etnaviv_ioctl_get_param()
360 gpu = priv->gpu[args->pipe]; in etnaviv_ioctl_wait_fence()
411 gpu = priv->gpu[args->pipe]; in etnaviv_ioctl_gem_wait()
439 gpu = priv->gpu[args->pipe]; in etnaviv_ioctl_pm_query_dom()
456 gpu = priv->gpu[args->pipe]; in etnaviv_ioctl_pm_query_sig()
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A Detnaviv_iommu_v2.c175 if (gpu->mmu_context) in etnaviv_iommuv2_restore_nonsec()
179 prefetch = etnaviv_buffer_config_mmuv2(gpu, in etnaviv_iommuv2_restore_nonsec()
182 etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer), in etnaviv_iommuv2_restore_nonsec()
184 etnaviv_gpu_wait_idle(gpu, 100); in etnaviv_iommuv2_restore_nonsec()
199 if (gpu->mmu_context) in etnaviv_iommuv2_restore_sec()
203 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_LOW, in etnaviv_iommuv2_restore_sec()
205 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_HIGH, in etnaviv_iommuv2_restore_sec()
224 etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer), in etnaviv_iommuv2_restore_sec()
226 etnaviv_gpu_wait_idle(gpu, 100); in etnaviv_iommuv2_restore_sec()
247 switch (gpu->sec_mode) { in etnaviv_iommuv2_restore()
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/linux-6.3-rc2/drivers/gpu/drm/msm/
A Dmsm_gpu.c61 if (gpu->core_clk && gpu->fast_rate) in enable_clk()
172 ret = gpu->funcs->hw_init(gpu); in msm_gpu_hw_init()
210 gpu->funcs->show(gpu, state, &p); in msm_gpu_devcoredump_read()
273 state = gpu->funcs->gpu_state_get(gpu); in msm_gpu_crashstate_capture()
428 gpu->funcs->recover(gpu); in recover_worker()
440 gpu->funcs->submit(gpu, submit); in recover_worker()
505 if (!gpu->funcs->progress(gpu, ring)) in made_progress()
788 gpu->funcs->submit(gpu, submit); in msm_gpu_submit()
802 return gpu->funcs->irq(gpu); in irq_handler()
947 gpu->aspace = gpu->funcs->create_address_space(gpu, pdev); in msm_gpu_init()
[all …]
A Dmsm_gpu_devfreq.c48 gpu->funcs->gpu_set_freq(gpu, opp, df->suspended); in msm_devfreq_target()
72 return gpu->funcs->gpu_get_freq(gpu); in get_freq()
99 busy_cycles = gpu->funcs->gpu_busy(gpu, &sample_rate); in msm_devfreq_get_dev_status()
190 gpu->cooling = NULL; in msm_devfreq_init()
215 if (!has_devfreq(gpu)) in msm_devfreq_cleanup()
227 if (!has_devfreq(gpu)) in msm_devfreq_resume()
231 df->busy_cycles = gpu->funcs->gpu_busy(gpu, &sample_rate); in msm_devfreq_resume()
243 if (!has_devfreq(gpu)) in msm_devfreq_suspend()
269 if (!has_devfreq(gpu)) in msm_devfreq_boost()
272 freq = get_freq(gpu); in msm_devfreq_boost()
[all …]
A Dmsm_gpu.h79 (struct msm_gpu *gpu);
459 if (rn >= gpu->nr_rings) in msm_gpu_convert_priority()
667 mutex_lock(&gpu->lock); in msm_gpu_crashstate_get()
669 if (gpu->crashstate) { in msm_gpu_crashstate_get()
671 state = gpu->crashstate; in msm_gpu_crashstate_get()
674 mutex_unlock(&gpu->lock); in msm_gpu_crashstate_get()
681 mutex_lock(&gpu->lock); in msm_gpu_crashstate_put()
683 if (gpu->crashstate) { in msm_gpu_crashstate_put()
684 if (gpu->funcs->gpu_state_put(gpu->crashstate)) in msm_gpu_crashstate_put()
685 gpu->crashstate = NULL; in msm_gpu_crashstate_put()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/msm/adreno/
A Da4xx_gpu.c180 return a4xx_idle(gpu); in a4xx_me_init()
325 gpu_write(gpu, REG_A4XX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova)); in a4xx_hw_init()
363 a4xx_dump(gpu); in a4xx_recover()
368 adreno_recover(gpu); in a4xx_recover()
376 DBG("%s", gpu->name); in a4xx_destroy()
388 if (!adreno_idle(gpu, gpu->rb[0])) in a4xx_idle()
418 msm_gpu_retire(gpu); in a4xx_irq()
569 adreno_dump(gpu); in a4xx_dump()
647 struct msm_gpu *gpu; in a4xx_gpu_init() local
685 if (!gpu->aspace) { in a4xx_gpu_init()
[all …]
A Da3xx_gpu.c109 return a3xx_idle(gpu); in a3xx_me_init()
119 DBG("%s", gpu->name); in a3xx_hw_init()
276 gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova)); in a3xx_hw_init()
364 a3xx_dump(gpu); in a3xx_recover()
369 adreno_recover(gpu); in a3xx_recover()
389 if (!adreno_idle(gpu, gpu->rb[0])) in a3xx_idle()
415 msm_gpu_retire(gpu); in a3xx_irq()
463 adreno_dump(gpu); in a3xx_dump()
519 struct msm_gpu *gpu; in a3xx_gpu_init() local
558 if (!gpu->aspace) { in a3xx_gpu_init()
[all …]
A Da5xx_gpu.c908 gpu_write64(gpu, REG_A5XX_CP_RB_BASE, gpu->rb[0]->iova); in a5xx_hw_init()
965 a5xx_flush(gpu, gpu->rb[0], true); in a5xx_hw_init()
966 if (!a5xx_idle(gpu, gpu->rb[0])) in a5xx_hw_init()
983 a5xx_flush(gpu, gpu->rb[0], true); in a5xx_hw_init()
984 if (!a5xx_idle(gpu, gpu->rb[0])) in a5xx_hw_init()
1018 a5xx_dump(gpu); in a5xx_recover()
1222 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); in a5xx_fault_detect_irq()
1246 kthread_queue_work(gpu->worker, &gpu->recover_work); in a5xx_fault_detect_irq()
1369 gpu->name, in a5xx_pm_resume()
1380 gpu->name); in a5xx_pm_resume()
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A Da5xx_power.c164 gpu_write(gpu, AGC_MSG_PAYLOAD(2), _get_mvolts(gpu, gpu->fast_rate)); in a530_lm_setup()
165 gpu_write(gpu, AGC_MSG_PAYLOAD(3), gpu->fast_rate / 1000000); in a530_lm_setup()
199 gpu_write(gpu, AGC_MSG_PAYLOAD(2), _get_mvolts(gpu, gpu->fast_rate)); in a540_lm_setup()
200 gpu_write(gpu, AGC_MSG_PAYLOAD(3), gpu->fast_rate / 1000000); in a540_lm_setup()
247 gpu->name); in a5xx_gpmu_init()
264 gpu->name); in a5xx_gpmu_init()
271 gpu->name, val); in a5xx_gpmu_init()
306 a530_lm_setup(gpu); in a5xx_power_init()
308 a540_lm_setup(gpu); in a5xx_power_init()
311 a5xx_pc_init(gpu); in a5xx_power_init()
[all …]
A Dadreno_gpu.h160 return gpu->revn == 225; in adreno_is_a225()
165 return gpu->revn == 305; in adreno_is_a305()
171 return gpu->revn == 307; in adreno_is_a306()
176 return gpu->revn == 320; in adreno_is_a320()
181 return gpu->revn == 330; in adreno_is_a330()
186 return adreno_is_a330(gpu) && (gpu->rev.patchid > 0); in adreno_is_a330v2()
191 return gpu->revn == 405; in adreno_is_a405()
256 return (gpu->revn == 640) || (gpu->revn == 680); in adreno_is_a640_family()
278 return gpu->revn == 615 || gpu->revn == 616 || gpu->revn == 618 || gpu->revn == 619; in adreno_is_a615_family()
283 return adreno_is_a660(gpu) || adreno_is_7c3(gpu); in adreno_is_a660_family()
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A Da2xx_gpu.c105 return a2xx_idle(gpu); in a2xx_me_init()
118 DBG("%s", gpu->name); in a2xx_hw_init()
219 gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova)); in a2xx_hw_init()
279 a2xx_dump(gpu); in a2xx_recover()
284 adreno_recover(gpu); in a2xx_recover()
302 if (!adreno_idle(gpu, gpu->rb[0])) in a2xx_idle()
351 msm_gpu_retire(gpu); in a2xx_irq()
452 adreno_dump(gpu); in a2xx_dump()
520 struct msm_gpu *gpu; in a2xx_gpu_init() local
554 if (!gpu->aspace) { in a2xx_gpu_init()
[all …]
A Da6xx_gpu.c1143 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova); in hw_init()
1202 a6xx_flush(gpu, gpu->rb[0]); in hw_init()
1203 if (!a6xx_idle(gpu, gpu->rb[0])) in hw_init()
1271 a6xx_dump(gpu); in a6xx_recover()
1381 gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu); in a6xx_fault_handler()
1427 kthread_queue_work(gpu->worker, &gpu->fault_work); in a6xx_fault_handler()
1479 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); in a6xx_fault_detect_irq()
1510 kthread_queue_work(gpu->worker, &gpu->recover_work); in a6xx_fault_detect_irq()
2048 if (gpu->aspace) in a6xx_gpu_init()
2049 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, in a6xx_gpu_init()
[all …]
A Da5xx_preempt.c66 empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring)); in get_next_ring()
80 struct drm_device *dev = gpu->dev; in a5xx_preempt_timer()
86 kthread_queue_work(gpu->worker, &gpu->recover_work); in a5xx_preempt_timer()
97 if (gpu->nr_rings == 1) in a5xx_preempt_trigger()
108 ring = get_next_ring(gpu); in a5xx_preempt_trigger()
180 gpu->name); in a5xx_preempt_irq()
181 kthread_queue_work(gpu->worker, &gpu->recover_work); in a5xx_preempt_irq()
203 if (gpu->nr_rings == 1) in a5xx_preempt_hw_init()
285 if (gpu->nr_rings <= 1) in a5xx_preempt_init()
294 a5xx_preempt_fini(gpu); in a5xx_preempt_init()
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A Da5xx_debugfs.c23 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA)); in pfp_print()
36 gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA)); in me_print()
49 gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA)); in meq_print()
79 show(priv->gpu, &p); in show()
97 struct msm_gpu *gpu = priv->gpu; in reset_set() local
110 mutex_lock(&gpu->lock); in reset_set()
130 gpu->needs_hw_init = true; in reset_set()
132 pm_runtime_get_sync(&gpu->pdev->dev); in reset_set()
133 gpu->funcs->recover(gpu); in reset_set()
135 pm_runtime_put_sync(&gpu->pdev->dev); in reset_set()
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A Da6xx_gpu_state.c124 SZ_1M, MSM_BO_WC, gpu->aspace, in a6xx_crashdumper_init()
216 gpu_write(gpu, ctrl0, reg); in vbif_debugbus_read()
219 gpu_write(gpu, ctrl1, i); in vbif_debugbus_read()
265 ptr += vbif_debugbus_read(gpu, in a6xx_get_vbif_debugbus_block()
271 ptr += vbif_debugbus_read(gpu, in a6xx_get_vbif_debugbus_block()
280 ptr += vbif_debugbus_read(gpu, in a6xx_get_vbif_debugbus_block()
398 a6xx_get_debugbus_block(gpu, in a6xx_get_debugbus()
421 a6xx_get_debugbus_block(gpu, in a6xx_get_debugbus()
905 a6xx_get_ahb_gpu_registers(gpu, in a6xx_get_registers()
910 a6xx_get_ahb_gpu_registers(gpu, in a6xx_get_registers()
[all …]
A Dadreno_gpu.c355 mutex_lock(&gpu->lock); in adreno_set_param()
509 VERB("%s", gpu->name); in adreno_hw_init()
543 return gpu->funcs->get_rptr(gpu, ring); in get_rptr()
548 return gpu->rb[0]; in adreno_active_ring()
559 gpu->funcs->pm_suspend(gpu); in adreno_recover()
560 gpu->funcs->pm_resume(gpu); in adreno_recover()
958 struct msm_gpu *gpu) in adreno_get_pwrlevels() argument
964 gpu->fast_rate = 0; in adreno_get_pwrlevels()
979 gpu->fast_rate = freq; in adreno_get_pwrlevels()
984 if (!gpu->fast_rate) { in adreno_get_pwrlevels()
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A Dadreno_device.c418 if (!gpu) { in adreno_load_gpu()
462 gpu->funcs->debugfs_init(gpu, dev->primary); in adreno_load_gpu()
463 gpu->funcs->debugfs_init(gpu, dev->render); in adreno_load_gpu()
467 return gpu; in adreno_load_gpu()
520 struct msm_gpu *gpu; in adreno_bind() local
546 if (IS_ERR(gpu)) { in adreno_bind()
563 gpu->funcs->destroy(gpu); in adreno_unbind()
631 return gpu->funcs->pm_resume(gpu); in adreno_runtime_resume()
645 return gpu->funcs->pm_suspend(gpu); in adreno_runtime_suspend()
684 if (!gpu) in adreno_system_suspend()
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A Da5xx_gpu.h135 int a5xx_power_init(struct msm_gpu *gpu);
136 void a5xx_gpmu_ucode_init(struct msm_gpu *gpu);
138 static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs, in spin_usecs() argument
143 if ((gpu_read(gpu, reg) & mask) == value) in spin_usecs()
154 bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
155 void a5xx_set_hwcg(struct msm_gpu *gpu, bool state);
157 void a5xx_preempt_init(struct msm_gpu *gpu);
158 void a5xx_preempt_hw_init(struct msm_gpu *gpu);
159 void a5xx_preempt_trigger(struct msm_gpu *gpu);
160 void a5xx_preempt_irq(struct msm_gpu *gpu);
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/linux-6.3-rc2/Documentation/gpu/
A Ddrm-kms-helpers.rst154 .. kernel-doc:: drivers/gpu/drm/drm_bridge.c
160 .. kernel-doc:: drivers/gpu/drm/drm_bridge.c
166 .. kernel-doc:: drivers/gpu/drm/drm_bridge.c
172 .. kernel-doc:: drivers/gpu/drm/drm_bridge.c
188 .. kernel-doc:: drivers/gpu/drm/drm_bridge.c
215 .. kernel-doc:: drivers/gpu/drm/drm_panel.c
221 .. kernel-doc:: drivers/gpu/drm/drm_panel.c
363 .. kernel-doc:: drivers/gpu/drm/drm_edid.c
401 .. kernel-doc:: drivers/gpu/drm/drm_rect.c
428 .. kernel-doc:: drivers/gpu/drm/drm_of.c
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A Di915.rst19 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
22 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
25 .. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c
31 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
34 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
37 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
40 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
46 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
49 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
55 .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
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