/linux-6.3-rc2/drivers/gpu/drm/radeon/ |
A D | r600_dma.c | 150 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); in r600_dma_resume() 236 u64 gpu_addr; in r600_dma_ring_test() local 243 gpu_addr = rdev->wb.gpu_addr + index; in r600_dma_ring_test() 254 radeon_ring_write(ring, lower_32_bits(gpu_addr)); in r600_dma_ring_test() 290 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_dma_fence_ring_emit() 317 u64 addr = semaphore->gpu_addr; in r600_dma_semaphore_ring_emit() 343 u64 gpu_addr; in r600_dma_ib_test() local 350 gpu_addr = rdev->wb.gpu_addr + index; in r600_dma_ib_test() 359 ib.ptr[1] = lower_32_bits(gpu_addr); in r600_dma_ib_test() 360 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in r600_dma_ib_test() [all …]
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A D | uvd_v4_2.c | 47 addr = (rdev->uvd.gpu_addr + 0x200) >> 3; in uvd_v4_2_resume() 49 addr = rdev->uvd.gpu_addr >> 3; in uvd_v4_2_resume() 67 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v4_2_resume() 71 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v4_2_resume()
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A D | uvd_v2_2.c | 43 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v2_2_fence_emit() 77 uint64_t addr = semaphore->gpu_addr; in uvd_v2_2_semaphore_emit() 113 addr = rdev->uvd.gpu_addr >> 3; in uvd_v2_2_resume() 130 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v2_2_resume() 134 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v2_2_resume()
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A D | cik_sdma.c | 155 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); in cik_sdma_ring_ib_execute() 203 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cik_sdma_fence_ring_emit() 232 u64 addr = semaphore->gpu_addr; in cik_sdma_semaphore_ring_emit() 651 u64 gpu_addr; in cik_sdma_ring_test() local 658 gpu_addr = rdev->wb.gpu_addr + index; in cik_sdma_ring_test() 669 radeon_ring_write(ring, lower_32_bits(gpu_addr)); in cik_sdma_ring_test() 670 radeon_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test() 708 u64 gpu_addr; in cik_sdma_ib_test() local 715 gpu_addr = rdev->wb.gpu_addr + index; in cik_sdma_ib_test() 727 ib.ptr[1] = lower_32_bits(gpu_addr); in cik_sdma_ib_test() [all …]
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A D | uvd_v1_0.c | 85 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v1_0_fence_emit() 121 addr = (rdev->uvd.gpu_addr >> 3) + 16; in uvd_v1_0_resume() 138 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v1_0_resume() 142 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v1_0_resume() 364 WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | in uvd_v1_0_start() 374 WREG32(UVD_RBC_RB_BASE, ring->gpu_addr); in uvd_v1_0_start() 487 radeon_ring_write(ring, ib->gpu_addr); in uvd_v1_0_ib_execute()
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A D | radeon_semaphore.c | 51 (*semaphore)->gpu_addr = radeon_sa_bo_gpu_addr((*semaphore)->sa_bo); in radeon_semaphore_create() 69 ring->last_semaphore_signal_addr = semaphore->gpu_addr; in radeon_semaphore_emit_signal() 86 ring->last_semaphore_wait_addr = semaphore->gpu_addr; in radeon_semaphore_emit_wait()
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A D | vce_v1_0.c | 218 uint64_t addr = rdev->vce.gpu_addr; in vce_v1_0_resume() 300 WREG32(VCE_RB_BASE_LO, ring->gpu_addr); in vce_v1_0_start() 301 WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vce_v1_0_start() 307 WREG32(VCE_RB_BASE_LO2, ring->gpu_addr); in vce_v1_0_start() 308 WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vce_v1_0_start()
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A D | radeon_trace.h | 177 __field(uint64_t, gpu_addr) 183 __entry->gpu_addr = sem->gpu_addr; 187 __entry->waiters, __entry->gpu_addr)
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A D | evergreen_dma.c | 44 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in evergreen_dma_fence_ring_emit() 88 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in evergreen_dma_ring_ib_execute() 89 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in evergreen_dma_ring_ib_execute()
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A D | radeon_object.h | 146 extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr); 148 u64 max_offset, u64 *gpu_addr); 175 return sa_bo->manager->gpu_addr + sa_bo->soffset; in radeon_sa_bo_gpu_addr()
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/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/ |
A D | amdgpu_ih.c | 69 ih->gpu_addr = dma_addr; in amdgpu_ih_ring_init() 89 &ih->ring_obj, &ih->gpu_addr, in amdgpu_ih_ring_init() 97 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; in amdgpu_ih_ring_init() 99 ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4; in amdgpu_ih_ring_init() 128 (void *)ih->ring, ih->gpu_addr); in amdgpu_ih_ring_fini() 131 amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr, in amdgpu_ih_ring_fini() 133 amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4); in amdgpu_ih_ring_fini() 134 amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4); in amdgpu_ih_ring_fini()
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A D | vcn_v2_0.c | 347 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume() 906 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v2_0_start_dpg_mode() 910 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode() 912 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode() 1070 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start() 1072 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start() 1792 uint64_t addr = table->gpu_addr; in vcn_v2_0_start_mmsch() 1954 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_sriov() 1957 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start_sriov() 1968 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_sriov() [all …]
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A D | vce_v4_0.c | 157 uint64_t addr = table->gpu_addr; in vce_v4_0_mmsch_start() 235 lower_32_bits(ring->gpu_addr)); in vce_v4_0_sriov_start() 237 upper_32_bits(ring->gpu_addr)); in vce_v4_0_sriov_start() 263 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start() 266 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_sriov_start() 273 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start() 276 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_sriov_start() 279 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start() 282 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_sriov_start() 662 (adev->vce.gpu_addr >> 8)); in vce_v4_0_mc_resume() [all …]
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A D | vcn_v2_5.c | 415 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume() 922 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v2_5_start_dpg_mode() 926 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_start_dpg_mode() 928 upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start_dpg_mode() 1106 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_start() 1108 upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start() 1144 uint64_t addr = table->gpu_addr; in vcn_v2_5_mmsch_start() 1294 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_sriov_start() 1297 upper_32_bits(ring->gpu_addr)); in vcn_v2_5_sriov_start() 1307 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_sriov_start() [all …]
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A D | si_dma.c | 74 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in si_dma_ring_emit_ib() 160 WREG32(DMA_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); in si_dma_start() 206 u64 gpu_addr; in si_dma_ring_test_ring() local 212 gpu_addr = adev->wb.gpu_addr + (index * 4); in si_dma_ring_test_ring() 221 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in si_dma_ring_test_ring() 222 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); in si_dma_ring_test_ring() 257 u64 gpu_addr; in si_dma_ring_test_ib() local 264 gpu_addr = adev->wb.gpu_addr + (index * 4); in si_dma_ring_test_ib() 274 ib.ptr[1] = lower_32_bits(gpu_addr); in si_dma_ring_test_ib() 275 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in si_dma_ring_test_ib() [all …]
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A D | vcn_v1_0.c | 318 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v1_0_mc_resume_spg_mode() 320 upper_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v1_0_mc_resume_spg_mode() 922 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v1_0_start_spg_mode() 926 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode() 928 upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode() 1080 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v1_0_start_dpg_mode() 1084 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start_dpg_mode() 1086 upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_dpg_mode() 1311 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode() 1313 upper_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode() [all …]
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A D | vcn_v3_0.c | 461 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v3_0_mc_resume() 1063 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v3_0_start_dpg_mode() 1067 lower_32_bits(ring->gpu_addr)); in vcn_v3_0_start_dpg_mode() 1069 upper_32_bits(ring->gpu_addr)); in vcn_v3_0_start_dpg_mode() 1244 lower_32_bits(ring->gpu_addr)); in vcn_v3_0_start() 1246 upper_32_bits(ring->gpu_addr)); in vcn_v3_0_start() 1348 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v3_0_start_sriov() 1351 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v3_0_start_sriov() 1394 rb_addr = ring->gpu_addr; in vcn_v3_0_start_sriov() 1408 rb_addr = ring->gpu_addr; in vcn_v3_0_start_sriov() [all …]
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A D | vce_v3_0.c | 283 WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr); in vce_v3_0_start() 284 WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start() 290 WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr); in vce_v3_0_start() 291 WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start() 297 WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr); in vce_v3_0_start() 298 WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start() 569 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume() 573 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume() 871 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib() 872 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib() [all …]
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A D | uvd_v7_0.c | 690 lower_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_mc_resume() 692 upper_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_mc_resume() 730 uint64_t addr = table->gpu_addr; in uvd_v7_0_mmsch_start() 832 lower_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_sriov_start() 834 upper_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_sriov_start() 1093 (upper_32_bits(ring->gpu_addr) >> 2)); in uvd_v7_0_start() 1097 lower_32_bits(ring->gpu_addr)); in uvd_v7_0_start() 1099 upper_32_bits(ring->gpu_addr)); in uvd_v7_0_start() 1329 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in uvd_v7_0_ring_emit_ib() 1332 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in uvd_v7_0_ring_emit_ib() [all …]
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A D | vcn_v4_0.c | 379 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v4_0_mc_resume() 381 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v4_0_mc_resume() 389 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v4_0_mc_resume() 391 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v4_0_mc_resume() 405 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v4_0_mc_resume() 1272 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v4_0_start_sriov() 1275 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v4_0_start_sriov() 1286 cache_addr = adev->vcn.inst[i].gpu_addr + offset; in vcn_v4_0_start_sriov() 1300 cache_addr = adev->vcn.inst[i].gpu_addr + offset + in vcn_v4_0_start_sriov() 1320 rb_enc_addr = ring_enc->gpu_addr; in vcn_v4_0_start_sriov() [all …]
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A D | sdma_v2_4.c | 259 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib() 260 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v2_4_ring_emit_ib() 544 u64 gpu_addr; in sdma_v2_4_ring_test_ring() local 550 gpu_addr = adev->wb.gpu_addr + (index * 4); in sdma_v2_4_ring_test_ring() 560 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring() 561 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring() 597 u64 gpu_addr; in sdma_v2_4_ring_test_ib() local 604 gpu_addr = adev->wb.gpu_addr + (index * 4); in sdma_v2_4_ring_test_ib() 615 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib() 616 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib() [all …]
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A D | cik_sdma.c | 233 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); in cik_sdma_ring_emit_ib() 476 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); in cik_sdma_gfx_resume() 612 u64 gpu_addr; in cik_sdma_ring_test_ring() local 618 gpu_addr = adev->wb.gpu_addr + (index * 4); in cik_sdma_ring_test_ring() 627 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in cik_sdma_ring_test_ring() 628 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test_ring() 664 u64 gpu_addr; in cik_sdma_ring_test_ib() local 671 gpu_addr = adev->wb.gpu_addr + (index * 4); in cik_sdma_ring_test_ib() 682 ib.ptr[1] = lower_32_bits(gpu_addr); in cik_sdma_ring_test_ib() 683 ib.ptr[2] = upper_32_bits(gpu_addr); in cik_sdma_ring_test_ib() [all …]
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A D | jpeg_v1_0.c | 62 val = lower_32_bits(ring->gpu_addr); in jpeg_v1_0_decode_ring_set_patch_ring() 68 val = upper_32_bits(ring->gpu_addr); in jpeg_v1_0_decode_ring_set_patch_ring() 311 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in jpeg_v1_0_decode_ring_emit_ib() 315 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in jpeg_v1_0_decode_ring_emit_ib() 323 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); in jpeg_v1_0_decode_ring_emit_ib() 327 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); in jpeg_v1_0_decode_ring_emit_ib() 530 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr)); in jpeg_v1_0_start() 531 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr)); in jpeg_v1_0_start()
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A D | sdma_v6_0.c | 266 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v6_0_ring_emit_ib() 876 u64 gpu_addr; in sdma_v6_0_ring_test_ring() local 885 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); in sdma_v6_0_ring_test_ring() 895 gpu_addr = adev->wb.gpu_addr + (index * 4); in sdma_v6_0_ring_test_ring() 908 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v6_0_ring_test_ring() 909 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in sdma_v6_0_ring_test_ring() 952 u64 gpu_addr; in sdma_v6_0_ring_test_ib() local 976 gpu_addr = adev->wb.gpu_addr + (index * 4); in sdma_v6_0_ring_test_ib() 988 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v6_0_ring_test_ib() 989 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v6_0_ring_test_ib() [all …]
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/linux-6.3-rc2/drivers/gpu/drm/amd/amdkfd/ |
A D | kfd_mqd_manager.c | 58 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr; in allocate_hiq_mqd() 83 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset; in allocate_sdma_mqd()
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