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Searched refs:i915_mmio_reg_offset (Results 1 – 25 of 47) sorted by relevance

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/linux-6.3-rc2/drivers/gpu/drm/i915/gvt/
A Dinterrupt.c157 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg) in regbase_to_irq_info()
335 regbase_to_iir(i915_mmio_reg_offset(info->reg_base))) in update_upstream_irq()
337 regbase_to_ier(i915_mmio_reg_offset(info->reg_base))); in update_upstream_irq()
364 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base); in update_upstream_irq()
370 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
372 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
454 reg_base = i915_mmio_reg_offset(info->reg_base); in propagate_event()
512 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) & in gen8_check_pending_irq()
523 reg_base = i915_mmio_reg_offset(info->reg_base); in gen8_check_pending_irq()
529 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) in gen8_check_pending_irq()
A Dedid.c383 if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) in intel_gvt_i2c_handle_gmbus_read()
385 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) in intel_gvt_i2c_handle_gmbus_read()
413 if (offset == i915_mmio_reg_offset(PCH_GMBUS0)) in intel_gvt_i2c_handle_gmbus_write()
415 else if (offset == i915_mmio_reg_offset(PCH_GMBUS1)) in intel_gvt_i2c_handle_gmbus_write()
417 else if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) in intel_gvt_i2c_handle_gmbus_write()
419 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) in intel_gvt_i2c_handle_gmbus_write()
A Dscheduler.c92 i915_mmio_reg_offset(EU_PERF_CNTL0), in sr_oa_regs()
93 i915_mmio_reg_offset(EU_PERF_CNTL1), in sr_oa_regs()
94 i915_mmio_reg_offset(EU_PERF_CNTL2), in sr_oa_regs()
95 i915_mmio_reg_offset(EU_PERF_CNTL3), in sr_oa_regs()
96 i915_mmio_reg_offset(EU_PERF_CNTL4), in sr_oa_regs()
97 i915_mmio_reg_offset(EU_PERF_CNTL5), in sr_oa_regs()
98 i915_mmio_reg_offset(EU_PERF_CNTL6), in sr_oa_regs()
114 i915_mmio_reg_offset(GEN8_OACTXCONTROL); in sr_oa_regs()
274 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = in save_ring_hw_state()
278 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = in save_ring_hw_state()
[all …]
A Dmmio_context.c228 *cs++ = i915_mmio_reg_offset(mmio->reg); in restore_context_mmio_for_inhibit()
258 *cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index)); in restore_render_mocs_control_for_inhibit()
285 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index)); in restore_render_mocs_l3cc_for_inhibit()
541 i915_mmio_reg_offset(mmio->reg), in switch_mmio()
A Dhandlers.c162 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
165 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
797 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) in ddi_buf_ctl_mmio_write()
879 end = i915_mmio_reg_offset(i915_end); in calc_index()
1074 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A))) in trigger_aux_channel_interrupt()
1077 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B))) in trigger_aux_channel_interrupt()
1080 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C))) in trigger_aux_channel_interrupt()
1083 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D))) in trigger_aux_channel_interrupt()
2132 ret = setup_mmio_info(gvt, i915_mmio_reg_offset(reg), \
2800 if (offset >= i915_mmio_reg_offset(block->offset) && in find_mmio_block()
[all …]
A Dgvt.h465 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
469 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
/linux-6.3-rc2/drivers/gpu/drm/i915/
A Di915_reg_defs.h146 #define i915_mmio_reg_offset(r) \ macro
148 #define i915_mmio_reg_equal(a, b) (i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b))
A Dintel_uncore.h329 u32 offset = i915_mmio_reg_offset(reg); \
339 u32 offset = i915_mmio_reg_offset(reg); \
512 readl(base + i915_mmio_reg_offset(reg))
514 writel(value, base + i915_mmio_reg_offset(reg))
A Di915_perf.c1255 *cs++ = i915_mmio_reg_offset(reg); in __store_reg_to_mem()
1848 *cs++ = i915_mmio_reg_offset(reg) + 4 * d; in save_restore_register()
1949 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)); in alloc_noa_wait()
1963 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)) + 4; in alloc_noa_wait()
1967 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)); in alloc_noa_wait()
1987 *cs++ = i915_mmio_reg_offset(mi_predicate_result); in alloc_noa_wait()
2030 *cs++ = i915_mmio_reg_offset(mi_predicate_result); in alloc_noa_wait()
2093 *cs++ = i915_mmio_reg_offset(reg_data[i].addr); in write_cs_mi_lri()
2342 u32 mmio = i915_mmio_reg_offset(reg); in oa_config_flex_reg()
2442 *cs++ = i915_mmio_reg_offset(flex->reg); in gen8_load_flex()
[all …]
A Dintel_device_info.c345 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS), in intel_ipver_early_init()
353 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY), in intel_ipver_early_init()
355 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA), in intel_ipver_early_init()
A Di915_ioctl.c55 u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw); in i915_reg_read_ioctl()
A Dintel_uncore.c1905 i915_mmio_reg_offset(reg))) in __unclaimed_reg_debug()
1919 i915_mmio_reg_offset(reg)); in __unclaimed_previous_reg_debug()
1996 u32 offset = i915_mmio_reg_offset(reg); \
2051 return __fwtable_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); in fwtable_reg_read_fw_domains()
2100 u32 offset = i915_mmio_reg_offset(reg); \
2139 return __fwtable_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); in fwtable_reg_write_fw_domains()
2209 d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set) + uncore->gsi_offset; in __fw_domain_init()
2210 d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack) + uncore->gsi_offset; in __fw_domain_init()
/linux-6.3-rc2/drivers/gpu/drm/i915/gt/
A Dintel_lrc.c1252 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_timestamp_wa()
1261 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); in gen12_emit_timestamp_wa()
1267 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); in gen12_emit_timestamp_wa()
1305 *cs++ = i915_mmio_reg_offset(RING_CMD_BUF_CCTL(0)); in gen12_emit_cmd_buf_wa()
1324 *cs++ = i915_mmio_reg_offset(XEHP_CULLBIT1); in dg2_emit_rcs_hang_wabb()
1328 *cs++ = i915_mmio_reg_offset(XEHP_CULLBIT2); in dg2_emit_rcs_hang_wabb()
1344 *cs++ = i915_mmio_reg_offset(DRAW_WATERMARK); in dg2_emit_draw_watermark_setting()
1582 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
1588 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
1597 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
[all …]
A Dselftest_lrc.c304 i915_mmio_reg_offset(RING_START(engine->mmio_base)), in live_lrc_fixed()
309 i915_mmio_reg_offset(RING_CTL(engine->mmio_base)), in live_lrc_fixed()
314 i915_mmio_reg_offset(RING_HEAD(engine->mmio_base)), in live_lrc_fixed()
319 i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)), in live_lrc_fixed()
324 i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)), in live_lrc_fixed()
329 i915_mmio_reg_offset(RING_BBSTATE(engine->mmio_base)), in live_lrc_fixed()
339 i915_mmio_reg_offset(RING_INDIRECT_CTX(engine->mmio_base)), in live_lrc_fixed()
364 i915_mmio_reg_offset(RING_BB_OFFSET(engine->mmio_base)), in live_lrc_fixed()
444 *cs++ = i915_mmio_reg_offset(RING_START(engine->mmio_base)); in __live_lrc_state()
451 *cs++ = i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)); in __live_lrc_state()
[all …]
A Dselftest_workarounds.c157 *cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i)); in read_nonprivs()
184 return i915_mmio_reg_offset(reg); in get_whitelist_reg()
465 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in whitelist_writable_count()
520 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in check_dirty_whitelist()
870 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in read_whitelisted_registers()
906 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in scrub_whitelisted_registers()
961 u32 offset = i915_mmio_reg_offset(reg); in find_reg()
965 i915_mmio_reg_offset(tbl->reg) == offset) in find_reg()
989 i915_mmio_reg_offset(reg), a, b); in result_eq()
1011 i915_mmio_reg_offset(reg), a); in result_neq()
[all …]
A Dintel_ring_submission.c666 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); in load_pd_dir()
670 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
675 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
680 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base)); in load_pd_dir()
728 *cs++ = i915_mmio_reg_offset( in mi_set_context()
783 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
790 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
825 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); in remap_l3_slice()
A Dintel_workarounds.c128 unsigned int addr = i915_mmio_reg_offset(wa->reg); in _wa_add()
167 i915_mmio_reg_offset(wa_->reg), in _wa_add()
186 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == in _wa_add()
187 i915_mmio_reg_offset(wa_[1].reg)); in _wa_add()
188 if (i915_mmio_reg_offset(wa_[1].reg) > in _wa_add()
189 i915_mmio_reg_offset(wa_[0].reg)) in _wa_add()
990 *cs++ = i915_mmio_reg_offset(wa->reg); in intel_engine_emit_ctx_wa()
1850 name, from, i915_mmio_reg_offset(wa->reg), in wa_verify()
2329 i915_mmio_reg_offset(wa->reg)); in intel_engine_apply_whitelist()
2335 i915_mmio_reg_offset(RING_NOPID(base))); in intel_engine_apply_whitelist()
[all …]
A Dselftest_rps.c102 *cs++ = i915_mmio_reg_offset(CS_GPR(i)); in create_spin_counter()
104 *cs++ = i915_mmio_reg_offset(CS_GPR(i)) + 4; in create_spin_counter()
109 *cs++ = i915_mmio_reg_offset(CS_GPR(INC)); in create_spin_counter()
124 *cs++ = i915_mmio_reg_offset(CS_GPR(COUNT)); in create_spin_counter()
207 i915_mmio_reg_offset(BXT_RP_STATE_CAP), in show_pstate_limits()
212 i915_mmio_reg_offset(GEN9_RP_STATE_LIMITS), in show_pstate_limits()
A Dselftest_mocs.c151 u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0)); in read_l3cc_table()
196 u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0)); in check_l3cc_table()
A Dgen7_renderclear.c400 batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7)); in emit_batch()
405 batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1)); in emit_batch()
A Dselftest_rc6.c147 *cs++ = i915_mmio_reg_offset(GEN8_RC6_CTX_INFO); in __live_rc6_ctx()
A Dgen8_engine_cs.c173 *cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset; in gen12_emit_aux_table_inv()
419 *cs++ = i915_mmio_reg_offset(RING_PREDICATE_RESULT(0)); in __xehp_emit_bb_start()
/linux-6.3-rc2/drivers/gpu/drm/i915/display/
A Dintel_dsb.c125 return prev_opcode == opcode && prev_reg == i915_mmio_reg_offset(reg); in intel_dsb_prev_ins_is_write()
171 i915_mmio_reg_offset(reg)); in intel_dsb_reg_write()
185 i915_mmio_reg_offset(reg); in intel_dsb_reg_write()
/linux-6.3-rc2/drivers/gpu/drm/i915/gt/uc/
A Dintel_guc.c181 guc->send_regs.base = i915_mmio_reg_offset(MEDIA_SOFT_SCRATCH(0)); in intel_guc_init_early()
184 guc->send_regs.base = i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0)); in intel_guc_init_early()
194 guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0)); in intel_guc_init_early()
A Dintel_uc.c417 i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET), in uc_init_wopcm()
420 i915_mmio_reg_offset(GUC_WOPCM_SIZE), in uc_init_wopcm()

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