/linux-6.3-rc2/Documentation/devicetree/bindings/arm/mediatek/ |
A D | mediatek,infracfg.yaml | 23 - mediatek,mt2701-infracfg 24 - mediatek,mt2712-infracfg 25 - mediatek,mt6765-infracfg 63 - mediatek,mt2701-infracfg 64 - mediatek,mt2712-infracfg 65 - mediatek,mt6795-infracfg 66 - mediatek,mt7622-infracfg 67 - mediatek,mt7986-infracfg 68 - mediatek,mt8135-infracfg 69 - mediatek,mt8173-infracfg [all …]
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A D | mediatek,mt8192-sys-clock.yaml | 21 - mediatek,mt8192-infracfg 50 infracfg: syscon@10001000 { 51 compatible = "mediatek,mt8192-infracfg", "syscon";
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/linux-6.3-rc2/drivers/soc/mediatek/ |
A D | mtk-infracfg.c | 28 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_set_bus_protection() argument 35 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, in mtk_infracfg_set_bus_protection() 38 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); in mtk_infracfg_set_bus_protection() 40 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_set_bus_protection() 59 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_clear_bus_protection() argument 66 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); in mtk_infracfg_clear_bus_protection() 68 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); in mtk_infracfg_clear_bus_protection() 70 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_clear_bus_protection() 79 struct regmap *infracfg; in mtk_infracfg_init() local 88 if (!IS_ERR(infracfg)) in mtk_infracfg_init() [all …]
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/linux-6.3-rc2/arch/arm64/boot/dts/mediatek/ |
A D | mt7986a.dtsi | 152 infracfg: infracfg@10001000 { label 249 <&infracfg CLK_INFRA_UART0_CK>; 264 <&infracfg CLK_INFRA_UART1_CK>; 277 <&infracfg CLK_INFRA_UART2_CK>; 291 <&infracfg CLK_INFRA_AP_DMA_CK>; 306 <&infracfg CLK_INFRA_SPI0_CK>, 320 <&infracfg CLK_INFRA_SPI1_CK>, 334 <&infracfg CLK_INFRA_IUSB_CK>, 356 <&infracfg CLK_INFRA_MSDC_CK>, 377 <&infracfg CLK_INFRA_IPCIE_CK>, [all …]
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A D | mt8183.dtsi | 809 infracfg: syscon@10001000 { label 869 mediatek,infracfg = <&infracfg>; 899 mediatek,infracfg = <&infracfg>; 921 mediatek,infracfg = <&infracfg>; 940 mediatek,infracfg = <&infracfg>; 951 mediatek,infracfg = <&infracfg>; 980 mediatek,infracfg = <&infracfg>; 990 mediatek,infracfg = <&infracfg>; 998 mediatek,infracfg = <&infracfg>; 1181 <&infracfg CLK_INFRA_SPI0>; [all …]
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A D | mt8167.dtsi | 26 infracfg: infracfg@10001000 { label 27 compatible = "mediatek,mt8167-infracfg", "syscon"; 54 mediatek,infracfg = <&infracfg>; 80 mediatek,infracfg = <&infracfg>; 91 mediatek,infracfg = <&infracfg>; 99 mediatek,infracfg = <&infracfg>;
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A D | mt8192.dtsi | 403 mediatek,infracfg = <&infracfg>; 411 mediatek,infracfg = <&infracfg>; 425 mediatek,infracfg = <&infracfg>; 466 mediatek,infracfg = <&infracfg>; 480 mediatek,infracfg = <&infracfg>; 490 mediatek,infracfg = <&infracfg>; 500 mediatek,infracfg = <&infracfg>; 509 mediatek,infracfg = <&infracfg>; 518 mediatek,infracfg = <&infracfg>; 529 mediatek,infracfg = <&infracfg>; [all …]
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A D | mt7622.dtsi | 75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>, 90 clocks = <&infracfg CLK_INFRA_MUX1_SEL>, 212 infracfg: infracfg@10000000 { label 213 compatible = "mediatek,mt7622-infracfg", 224 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>; 226 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>; 249 infracfg = <&infracfg>; 258 clocks = <&infracfg CLK_INFRA_IRRX_PD>, 303 clocks = <&infracfg CLK_INFRA_TRNG>; 623 clocks = <&infracfg CLK_INFRA_AUDIO_PD>, [all …]
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A D | mt8173.dtsi | 159 clocks = <&infracfg CLK_INFRA_CA53SEL>, 174 clocks = <&infracfg CLK_INFRA_CA53SEL>, 189 clocks = <&infracfg CLK_INFRA_CA72SEL>, 355 infracfg: power-controller@10001000 { label 481 mediatek,infracfg = <&infracfg>; 515 mediatek,infracfg = <&infracfg>; 544 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 552 clocks = <&infracfg CLK_INFRA_CEC>; 580 clocks = <&infracfg CLK_INFRA_M4U>; 582 mediatek,infracfg = <&infracfg>; [all …]
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A D | mt8516.dtsi | 57 clocks = <&infracfg CLK_IFR_MUX1_SEL>, 70 clocks = <&infracfg CLK_IFR_MUX1_SEL>, 83 clocks = <&infracfg CLK_IFR_MUX1_SEL>, 96 clocks = <&infracfg CLK_IFR_MUX1_SEL>, 188 infracfg: infracfg@10001000 { label 189 compatible = "mediatek,mt8516-infracfg", "syscon";
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A D | mt2712e.dtsi | 252 infracfg: syscon@10001000 { label 253 compatible = "mediatek,mt2712-infracfg", "syscon"; 292 infracfg = <&infracfg>; 318 clocks = <&infracfg CLK_INFRA_AO_SPI1>; 329 clocks = <&infracfg CLK_INFRA_M4U>; 331 mediatek,infracfg = <&infracfg>; 347 clocks = <&infracfg CLK_INFRA_M4U>; 349 mediatek,infracfg = <&infracfg>; 662 <&infracfg CLK_INFRA_AO_SPI0>;
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/linux-6.3-rc2/Documentation/devicetree/bindings/sound/ |
A D | mt8192-afe-pcm.yaml | 30 mediatek,infracfg: 32 description: The phandle of the mediatek infracfg controller 63 - mediatek,infracfg 85 mediatek,infracfg = <&infracfg>; 91 <&infracfg CLK_INFRA_AUDIO>, 92 <&infracfg CLK_INFRA_AUDIO_26M_B>;
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A D | mt8186-afe-pcm.yaml | 32 mediatek,infracfg: 34 description: The phandle of the mediatek infracfg controller 102 - mediatek,infracfg 121 mediatek,infracfg = <&infracfg>;
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A D | mtk-btcvsd-snd.txt | 7 - mediatek,infracfg: the phandles of INFRASYS 22 mediatek,infracfg = <&infrasys>;
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/linux-6.3-rc2/drivers/net/wireless/mediatek/mt76/mt7615/ |
A D | soc.c | 23 dev->infracfg = syscon_regmap_lookup_by_phandle(np, "mediatek,infracfg"); in mt7622_wmac_init() 24 if (IS_ERR(dev->infracfg)) { in mt7622_wmac_init() 26 return PTR_ERR(dev->infracfg); in mt7622_wmac_init()
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/linux-6.3-rc2/Documentation/devicetree/bindings/pci/ |
A D | mediatek-pcie-gen3.yaml | 212 clocks = <&infracfg 44>, 213 <&infracfg 40>, 214 <&infracfg 43>, 215 <&infracfg 97>, 216 <&infracfg 99>, 217 <&infracfg 111>;
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/linux-6.3-rc2/Documentation/devicetree/bindings/soc/mediatek/ |
A D | scpsys.txt | 32 - infracfg: must contain a phandle to the infracfg controller 65 infracfg = <&infracfg>;
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/linux-6.3-rc2/Documentation/devicetree/bindings/cpufreq/ |
A D | cpufreq-mediatek.txt | 70 clocks = <&infracfg CLK_INFRA_CPUSEL>, 192 clocks = <&infracfg CLK_INFRA_CA53SEL>, 204 clocks = <&infracfg CLK_INFRA_CA53SEL>, 216 clocks = <&infracfg CLK_INFRA_CA72SEL>, 228 clocks = <&infracfg CLK_INFRA_CA72SEL>,
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/linux-6.3-rc2/Documentation/devicetree/bindings/iommu/ |
A D | mediatek,iommu.yaml | 106 mediatek,infracfg: 108 description: The phandle to the mediatek infracfg syscon 190 - mediatek,infracfg 214 clocks = <&infracfg CLK_INFRA_M4U>; 216 mediatek,infracfg = <&infracfg>;
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/linux-6.3-rc2/Documentation/devicetree/bindings/power/ |
A D | mediatek,power-controller.yaml | 114 mediatek,infracfg: 174 mediatek,infracfg = <&infracfg>; 208 mediatek,infracfg = <&infracfg>;
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/linux-6.3-rc2/arch/arm/boot/dts/ |
A D | mt7629.dtsi | 81 infracfg: syscon@10000000 { label 82 compatible = "mediatek,mt7629-infracfg", "syscon"; 102 infracfg = <&infracfg>; 133 clocks = <&infracfg CLK_INFRA_TRNG_PD>; 473 mediatek,infracfg = <&infracfg>;
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A D | mt7623.dtsi | 80 clocks = <&infracfg CLK_INFRA_CPUSEL>, 92 clocks = <&infracfg CLK_INFRA_CPUSEL>, 104 clocks = <&infracfg CLK_INFRA_CPUSEL>, 116 clocks = <&infracfg CLK_INFRA_CPUSEL>, 234 infracfg: syscon@10001000 { label 236 "mediatek,mt2701-infracfg", 276 infracfg = <&infracfg>; 306 clocks = <&infracfg CLK_INFRA_PMICSPI>, 307 <&infracfg CLK_INFRA_PMICWRAP>; 315 clocks = <&infracfg CLK_INFRA_IRRX>; [all …]
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A D | mt8135.dtsi | 133 infracfg: infracfg@10001000 { label 136 compatible = "mediatek,mt8135-infracfg", "syscon"; 184 resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
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/linux-6.3-rc2/Documentation/devicetree/bindings/spmi/ |
A D | mtk,spmi-mtk-pmif.yaml | 67 clocks = <&infracfg CLK_INFRA_PMIC_AP>, 68 <&infracfg CLK_INFRA_PMIC_TMR>,
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/linux-6.3-rc2/Documentation/devicetree/bindings/phy/ |
A D | mediatek,ufs-phy.yaml | 63 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 64 <&infracfg CLK_INFRA_UFS_MP_SAP_BCLK>;
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