| /linux-6.3-rc2/Documentation/arm64/ |
| A D | legacy_instructions.rst | 2 Legacy instructions
6 emulation of instructions which have been deprecated, or obsoleted in
18 Generates undefined instruction abort. Default for instructions that
27 instructions, .e.g., CP15 barriers
34 instructions. Using hardware execution generally provides better
36 about the use of the deprecated instructions.
39 architecture. Deprecated instructions should default to emulation
40 while obsolete instructions must be undefined by default.
45 Supported legacy instructions
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| A D | pointer-authentication.rst | 25 The extension adds instructions to insert a valid PAC into a pointer,
30 A subset of these instructions have been allocated from the HINT
32 these instructions behave as NOPs. Applications and libraries using
33 these instructions operate correctly regardless of the presence of the
57 with HINT space pointer authentication instructions protecting
107 register. Any attempt to use the Pointer Authentication instructions will
128 instructions to sign and authenticate function pointers and other pointers
135 but before executing any PAC instructions.
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| /linux-6.3-rc2/Documentation/bpf/ |
| A D | instruction-set.rst | 66 Note that most instructions do not use all of the fields.
106 Arithmetic and jump instructions
134 Arithmetic instructions
192 Byte swap instructions argument
198 The byte swap instructions operate on the destination register
224 Jump instructions
254 Load and store instructions
271 BPF_IMM 0x00 64-bit immediate instructions `64-bit immediate instructions`_
293 instructions that transfer data between a register and memory.
370 64-bit immediate instructions
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| A D | linux-notes.rst | 10 Byte swap instructions
15 Legacy BPF Packet access instructions
18 …d in the `ISA standard documentation <instruction-set.rst#legacy-bpf-packet-access-instructions>`_,
19 Linux has special eBPF instructions for access to packet data that have been
23 The instructions come in two forms: ``BPF_ABS | <size> | BPF_LD`` and
26 These instructions are used to access packet data and can only be used when
32 These instructions have seven implicit operands:
41 These instructions have an implicit program exit condition as well. If an
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| A D | bpf_design_QA.rst | 93 It's the maximum number of instructions that the unprivileged bpf
95 Like the maximum number of instructions that can be explored during
119 Q: LD_ABS and LD_IND instructions vs C code
129 Q: BPF instructions mapping not one-to-one to native CPU
131 Q: It seems not all BPF instructions are one-to-one to native CPU.
154 of LD_ABS insn). Those instructions need to invoke epilogue and
161 due to lack of these compare instructions and they were added.
162 These two instructions is a perfect example what kind of new BPF
163 instructions are acceptable and can be added in the future.
164 These two already had equivalent instructions in native CPUs.
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| /linux-6.3-rc2/drivers/watchdog/ |
| A D | wdat_wdt.c | 119 if (action >= ARRAY_SIZE(wdat->instructions)) in wdat_wdt_run_action()
122 if (!wdat->instructions[action]) in wdat_wdt_run_action()
376 struct list_head *instructions; in wdat_wdt_probe() local
423 instructions = wdat->instructions[action]; in wdat_wdt_probe()
424 if (!instructions) { in wdat_wdt_probe()
425 instructions = devm_kzalloc(dev, in wdat_wdt_probe()
426 sizeof(*instructions), in wdat_wdt_probe()
428 if (!instructions) in wdat_wdt_probe()
431 INIT_LIST_HEAD(instructions); in wdat_wdt_probe()
432 wdat->instructions[action] = instructions; in wdat_wdt_probe()
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| /linux-6.3-rc2/tools/perf/Documentation/ |
| A D | itrace.txt | 1 i synthesize instructions events
33 for instructions events can be specified in units of:
35 i instructions
41 Also the call chain size (default 16, max. 1024) for instructions or
45 instructions or transactions events can be specified.
51 It is also possible to skip events generated (instructions, branches, transactions,
56 skips the first million instructions.
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| A D | intel-hybrid.txt | 29 [Fixed Counter: Counts the number of instructions retired. Unit: cpu_atom]
31 [Number of instructions retired. Fixed Counter - architectural event. Unit: cpu_core]
184 cpu_core/instructions/,
185 cpu_atom/instructions/,
199 perf stat -e cpu_core/cycles/,cpu_atom/instructions/
200 perf stat -e '{cpu_core/cycles/,cpu_core/instructions/}'
202 But '{cpu_core/cycles/,cpu_atom/instructions/}' will return
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| /linux-6.3-rc2/Documentation/arm/ |
| A D | swp_emulation.rst | 4 ARMv6 architecture deprecates use of the SWP/SWPB instructions, and recommeds
5 moving to the load-locked/store-conditional instructions LDREX and STREX.
8 instructions, triggering an undefined instruction exception when executed.
9 Trapped instructions are emulated using an LDREX/STREX or LDREXB/STREXB
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| A D | kernel_mode_neon.rst | 7 * Use only NEON instructions, or VFP instructions that don't rely on support
19 It is possible to use NEON instructions (and in some cases, VFP instructions) in
24 may call schedule()], as NEON or VFP instructions will be executed in a
43 should be called before any kernel mode NEON or VFP instructions are issued.
74 Such software assistance is currently not implemented for VFP instructions
82 kernel_neon_end(), i.e., that it is only allowed to issue NEON/VFP instructions
84 instructions of its own at -O3 level if -mfpu=neon is selected, and even if the
86 instructions appearing in unexpected places if no special care is taken.
98 both NEON and VFP instructions will only ever appear in designated compilation
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| /linux-6.3-rc2/Documentation/x86/x86_64/ |
| A D | fsgs.rst | 69 Accessing FS/GS base with the FSGSBASE instructions
73 instructions to access the FS and GS base registers directly from user
74 space. These instructions are also supported on AMD Family 17H CPUs. The
75 following instructions are available:
90 FSGSBASE instructions enablement argument
92 The instructions are enumerated in CPUID leaf 7, bit 0 of EBX. If
95 The availability of the instructions does not enable them
103 instructions will fault with a #UD exception.
107 kernel has FSGSBASE instructions enabled and applications can use them.
125 FSGSBASE instructions compiler support argument
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| /linux-6.3-rc2/tools/testing/selftests/powerpc/pmu/ |
| A D | count_instructions.c | 29 static int do_count_loop(struct event *events, u64 instructions, in do_count_loop() argument
38 thirty_two_instruction_loop(instructions >> 5); in do_count_loop()
45 expected = instructions + overhead; in do_count_loop()
53 printf("Looped for %llu instructions, overhead %llu\n", instructions, overhead); in do_count_loop()
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| A D | count_stcx_fail.c | 29 static int do_count_loop(struct event *events, u64 instructions, in do_count_loop() argument
39 thirty_two_instruction_loop_with_ll_sc(instructions >> 5, &dummy); in do_count_loop()
47 expected = instructions + overhead + (events[2].result.value * 10); in do_count_loop()
57 printf("Looped for %llu instructions, overhead %llu\n", instructions, overhead); in do_count_loop()
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| /linux-6.3-rc2/tools/perf/tests/shell/ |
| A D | stat+shadow_stat.sh | 15 perf stat -a --no-big-num -e cycles,instructions sleep 1 2>&1 | \
16 grep -e cycles -e instructions | \
46 perf stat -a -A --no-big-num -e cycles,instructions sleep 1 2>&1 | \
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| /linux-6.3-rc2/tools/testing/selftests/powerpc/pmu/ebb/ |
| A D | instruction_count_test.c | 25 static int do_count_loop(struct event *event, uint64_t instructions, in do_count_loop() argument
37 thirty_two_instruction_loop(instructions >> 5); in do_count_loop()
46 expected = instructions + overhead; in do_count_loop()
51 printf("Looped for %lu instructions, overhead %lu\n", instructions, overhead); in do_count_loop()
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| /linux-6.3-rc2/arch/sparc/crypto/ |
| A D | Kconfig | 37 Architecture: sparc64 using crypto instructions, when available
57 Architecture: sparc64 using crypto instructions, when available
67 Architecture: sparc64 using crypto instructions, when available
77 Architecture: sparc64 using crypto instructions
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| /linux-6.3-rc2/tools/memory-model/ |
| A D | linux-kernel.bell | 20 instructions R[{'once,'acquire,'noreturn}]
21 instructions W[{'once,'release}]
22 instructions RMW[{'once,'acquire,'release}]
35 instructions F[Barriers]
39 instructions SRCU[SRCU]
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| /linux-6.3-rc2/Documentation/virt/kvm/ |
| A D | ppc-pv.rst | 9 instructions and can emulate them accordingly.
12 instructions that needlessly return us to the hypervisor even though they
15 This is what the PPC PV interface helps with. It takes privileged instructions
35 'hypercall-instructions'. This property contains at most 4 opcodes that make
36 up the hypercall. To call a hypercall, just call these instructions.
138 Patched instructions
141 The "ld" and "std" instructions are transformed to "lwz" and "stw" instructions
147 also act on the shared page. So calling privileged instructions still works as
187 Some instructions require more logic to determine what's going on than a load
189 RAM around where we can live translate instructions to. What happens is the
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| /linux-6.3-rc2/arch/mips/crypto/ |
| A D | Kconfig | 31 Architecture: mips OCTEON using crypto instructions, when available
51 Architecture: mips OCTEON using crypto instructions, when available
61 Architecture: mips OCTEON using crypto instructions, when available
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| /linux-6.3-rc2/Documentation/virt/ |
| A D | paravirt_ops.rst | 16 corresponding to low level critical instructions and high level
28 Usually these operations correspond to low level critical instructions. They
34 because they include sensitive instructions or some of code paths in
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| /linux-6.3-rc2/arch/arm/kernel/ |
| A D | phys2virt.S | 41 mov r0, r3, lsr #21 @ constant for add/sub instructions
77 @ In the non-LPAE case, all patchable instructions are MOVW
78 @ instructions, where we need to patch in the offset into the
131 @ in BE8, we load data in BE, but instructions still in LE
155 @ In the non-LPAE case, all patchable instructions are ADD or SUB
156 @ instructions, where we need to patch in the offset into the
173 @ instructions based on bits 23:22 of the opcode, and ADD/SUB can be
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| /linux-6.3-rc2/Documentation/powerpc/ |
| A D | elf_hwcaps.rst | 48 The Power ISA uses the term "facility" to describe a class of instructions,
52 instructions that can be used differ between the v3.0B and v3.1B ISA
59 classes of instructions and operating modes which may be optional or
96 The processor has a unified L1 cache for instructions and data, as
138 instructions with the sequence (as described in, e.g., POWER9 Processor
201 v2.07 crypto instructions are available.
213 quad-precision instructions and data types.
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| /linux-6.3-rc2/arch/nios2/platform/ |
| A D | Kconfig.platform | 53 comment "Nios II instructions"
82 bool "Enable BMX instructions"
86 the BMX Bit Manipulation Extension instructions. Enables
90 bool "Enable CDX instructions"
94 the CDX Bit Manipulation Extension instructions. Enables
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| /linux-6.3-rc2/drivers/media/pci/tw68/ |
| A D | tw68-risc.c | 137 u32 instructions, fields; in tw68_risc_buffer() local
151 instructions = fields * (1 + (((bpl + padding) * lines) / in tw68_risc_buffer()
153 buf->size = instructions * 8; in tw68_risc_buffer()
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| /linux-6.3-rc2/arch/m68k/ifpsp060/ |
| A D | fplsp.doc | 36 FP instructions not implemented in 68060 hardware. These
37 instructions normally take exception vector #11
40 By re-compiling a program that uses these instructions, and
42 instructions, a program can avoid the overhead associated
110 this exception using implemented floating-point instructions.
120 The package does not attempt to correctly emulate instructions
126 subroutine calls for all fp instructions. The code does NOT emulate
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