Home
last modified time | relevance | path

Searched refs:intel_de_read (Results 1 – 25 of 60) sorted by relevance

123

/linux-6.3-rc2/drivers/gpu/drm/i915/display/
A Dintel_fdi.c342 temp = intel_de_read(dev_priv, reg); in intel_fdi_normal_train()
353 temp = intel_de_read(dev_priv, reg); in intel_fdi_normal_train()
396 temp = intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
400 intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
405 temp = intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
413 temp = intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
443 temp = intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
449 temp = intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
503 temp = intel_de_read(dev_priv, reg); in gen6_fdi_link_train()
513 temp = intel_de_read(dev_priv, reg); in gen6_fdi_link_train()
[all …]
A Dintel_pch_display.c112 u32 val = intel_de_read(dev_priv, hdmi_reg); in ibx_sanitize_pch_hdmi_port()
131 u32 val = intel_de_read(dev_priv, dp_reg); in ibx_sanitize_pch_dp_port()
255 val = intel_de_read(dev_priv, reg); in ilk_enable_pch_transcoder()
268 val = intel_de_read(dev_priv, reg); in ilk_enable_pch_transcoder()
320 val = intel_de_read(dev_priv, reg); in ilk_disable_pch_transcoder()
331 val = intel_de_read(dev_priv, reg); in ilk_disable_pch_transcoder()
380 temp = intel_de_read(dev_priv, PCH_DPLL_SEL); in ilk_pch_enable()
421 temp = intel_de_read(dev_priv, reg); in ilk_pch_enable()
464 temp = intel_de_read(dev_priv, reg); in ilk_pch_post_disable()
526 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL); in ilk_pch_get_config()
[all …]
A Dintel_combo_phy.c59 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
85 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy)); in icl_set_procmon_ref_values()
98 u32 val = intel_de_read(dev_priv, reg); in check_phy_reg()
162 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & in icl_combo_phy_enabled()
311 val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy)); in intel_combo_phy_power_up_lanes()
342 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); in icl_combo_phys_init()
370 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy)); in icl_combo_phys_init()
375 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); in icl_combo_phys_init()
379 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); in icl_combo_phys_init()
413 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); in icl_combo_phys_uninit()
[all …]
A Dicl_dsi.c285 tmp = intel_de_read(dev_priv, in dsi_program_swing_and_deemphasis()
305 dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1); in configure_dual_link_mode()
326 dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2); in configure_dual_link_mode()
451 tmp = intel_de_read(dev_priv, in gen11_dsi_config_phy_lanes_sequence()
474 tmp = intel_de_read(dev_priv, in gen11_dsi_config_phy_lanes_sequence()
481 tmp = intel_de_read(dev_priv, in gen11_dsi_config_phy_lanes_sequence()
611 tmp = intel_de_read(dev_priv, in gen11_dsi_setup_dphy_timings()
620 tmp = intel_de_read(dev_priv, in gen11_dsi_setup_dphy_timings()
827 tmp = intel_de_read(dev_priv, in gen11_dsi_configure_transcoder()
1128 tmp = intel_de_read(dev_priv, UTIL_PIN_CTL); in gen11_dsi_config_util_pin()
[all …]
A Dvlv_dsi.c123 u32 val = intel_de_read(dev_priv, reg); in read_data()
342 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in glk_dsi_enable_io()
354 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in glk_dsi_enable_io()
634 val = intel_de_read(dev_priv, port_ctrl); in vlv_dsi_clear_device_ready()
655 temp = intel_de_read(dev_priv, in intel_dsi_port_enable()
677 temp = intel_de_read(dev_priv, port_ctrl); in intel_dsi_port_enable()
715 temp = intel_de_read(dev_priv, port_ctrl); in intel_dsi_port_disable()
1065 u32 tmp = intel_de_read(dev_priv, in intel_dsi_get_hw_state()
1141 intel_de_read(dev_priv, in bxt_dsi_get_pipe_config()
1144 intel_de_read(dev_priv, in bxt_dsi_get_pipe_config()
[all …]
A Dintel_display_power_well.c359 val = intel_de_read(dev_priv, regs->driver); in hsw_power_well_enable()
388 val = intel_de_read(dev_priv, regs->driver); in hsw_power_well_disable()
405 val = intel_de_read(dev_priv, regs->driver); in icl_combo_phy_aux_power_well_enable()
441 val = intel_de_read(dev_priv, regs->driver); in icl_combo_phy_aux_power_well_disable()
515 val = intel_de_read(dev_priv, regs->driver); in icl_tc_phy_aux_power_well_enable()
587 val = intel_de_read(dev_priv, regs->driver); in hsw_power_well_enabled()
597 val |= intel_de_read(dev_priv, regs->bios); in hsw_power_well_enabled()
608 intel_de_read(dev_priv, DC_STATE_EN) & in assert_can_enable_dc9()
660 v = intel_de_read(dev_priv, DC_STATE_EN); in gen9_write_dc_state()
753 val = intel_de_read(dev_priv, DC_STATE_EN); in gen9_set_dc_state()
[all …]
A Dintel_backlight.c383 tmp = intel_de_read(i915, BLC_PWM_CTL2); in i965_disable_backlight()
414 val = intel_de_read(i915, UTIL_PIN_CTL); in bxt_disable_backlight()
579 ctl = intel_de_read(i915, BLC_PWM_CTL); in i9xx_enable_backlight()
619 ctl2 = intel_de_read(i915, BLC_PWM_CTL2); in i965_enable_backlight()
686 val = intel_de_read(i915, UTIL_PIN_CTL); in bxt_enable_backlight()
1309 ctl = intel_de_read(i915, BLC_PWM_CTL); in i9xx_setup_backlight()
1347 ctl2 = intel_de_read(i915, BLC_PWM_CTL2); in i965_setup_backlight()
1351 ctl = intel_de_read(i915, BLC_PWM_CTL); in i965_setup_backlight()
1407 pwm_ctl = intel_de_read(i915, in bxt_setup_backlight()
1412 val = intel_de_read(i915, UTIL_PIN_CTL); in bxt_setup_backlight()
[all …]
A Dintel_dpll_mgr.c452 val = intel_de_read(dev_priv, PCH_DPLL(id)); in ibx_pch_dpll_get_hw_state()
631 val = intel_de_read(dev_priv, SPLL_CTL); in hsw_ddi_spll_disable()
676 val = intel_de_read(dev_priv, SPLL_CTL); in hsw_ddi_spll_get_hw_state()
1243 val = intel_de_read(dev_priv, DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
1319 val = intel_de_read(dev_priv, DPLL_CTRL1); in skl_ddi_pll_get_hw_state()
1357 val = intel_de_read(dev_priv, DPLL_CTRL1); in skl_ddi_dpll0_get_hw_state()
2106 intel_de_read(dev_priv, in bxt_ddi_pll_get_hw_state()
3413 val = intel_de_read(dev_priv, enable_reg); in mg_pll_get_hw_state()
3548 val = intel_de_read(dev_priv, enable_reg); in icl_pll_get_hw_state()
3771 val = intel_de_read(dev_priv, enable_reg); in icl_pll_power_enable()
[all …]
A Dintel_crt.c85 val = intel_de_read(dev_priv, adpa_reg); in intel_crt_port_enabled()
122 tmp = intel_de_read(dev_priv, crt->adpa_reg); in intel_crt_get_flags()
494 adpa = intel_de_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
545 adpa = intel_de_read(dev_priv, crt->adpa_reg); in valleyview_crt_detect_hotplug()
596 stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT); in intel_crt_detect_hotplug()
696 save_bclrpat = intel_de_read(dev_priv, BCLRPAT(pipe)); in intel_crt_load_detect()
697 save_vtotal = intel_de_read(dev_priv, VTOTAL(pipe)); in intel_crt_load_detect()
698 vblank = intel_de_read(dev_priv, VBLANK(pipe)); in intel_crt_load_detect()
733 u32 vsync = intel_de_read(dev_priv, VSYNC(pipe)); in intel_crt_load_detect()
947 adpa = intel_de_read(dev_priv, crt->adpa_reg); in intel_crt_reset()
[all …]
A Dintel_pps.c603 intel_de_read(dev_priv, pp_stat_reg), in wait_panel_status()
604 intel_de_read(dev_priv, pp_ctrl_reg)); in wait_panel_status()
612 intel_de_read(dev_priv, pp_stat_reg), in wait_panel_status()
613 intel_de_read(dev_priv, pp_ctrl_reg)); in wait_panel_status()
754 intel_de_read(dev_priv, pp_stat_reg), in intel_pps_vdd_on_unlocked()
755 intel_de_read(dev_priv, pp_ctrl_reg)); in intel_pps_vdd_on_unlocked()
826 intel_de_read(dev_priv, pp_stat_reg), in intel_pps_vdd_off_sync_unlocked()
827 intel_de_read(dev_priv, pp_ctrl_reg)); in intel_pps_vdd_off_sync_unlocked()
1551 intel_de_read(dev_priv, regs.pp_on), in pps_init_registers()
1552 intel_de_read(dev_priv, regs.pp_off), in pps_init_registers()
[all …]
A Dintel_dpio_phy.c334 if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) & in bxt_ddi_phy_is_enabled()
392 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); in _bxt_ddi_phy_init()
413 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW9(phy)); in _bxt_ddi_phy_init()
418 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW10(phy)); in _bxt_ddi_phy_init()
453 val = intel_de_read(dev_priv, BXT_PORT_REF_DW8(phy)); in _bxt_ddi_phy_init()
461 val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)); in _bxt_ddi_phy_init()
473 val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)); in bxt_ddi_phy_uninit()
477 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); in bxt_ddi_phy_uninit()
517 val = intel_de_read(dev_priv, reg); in __phy_reg_verify_state()
620 u32 val = intel_de_read(dev_priv, in bxt_ddi_phy_set_lane_optim_mask()
[all …]
A Dintel_lvds.c92 val = intel_de_read(dev_priv, lvds_reg); in intel_lvds_port_enabled()
132 tmp = intel_de_read(dev_priv, lvds_encoder->reg); in intel_lvds_get_config()
150 tmp = intel_de_read(dev_priv, PFIT_CONTROL); in intel_lvds_get_config()
165 val = intel_de_read(dev_priv, PP_ON_DELAYS(0)); in intel_lvds_pps_get_hw_state()
170 val = intel_de_read(dev_priv, PP_OFF_DELAYS(0)); in intel_lvds_pps_get_hw_state()
174 val = intel_de_read(dev_priv, PP_DIVISOR(0)); in intel_lvds_pps_get_hw_state()
211 val = intel_de_read(dev_priv, PP_CONTROL(0)); in intel_lvds_pps_init_hw()
323 intel_de_read(dev_priv, PP_CONTROL(0)) | PANEL_POWER_ON); in intel_enable_lvds()
342 intel_de_read(dev_priv, PP_CONTROL(0)) & ~PANEL_POWER_ON); in intel_disable_lvds()
811 val = intel_de_read(dev_priv, lvds_encoder->reg); in compute_is_dual_link_lvds()
[all …]
A Dintel_pch_refclk.c17 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2); in lpt_fdi_reset_mphy()
21 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) & in lpt_fdi_reset_mphy()
25 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2); in lpt_fdi_reset_mphy()
29 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) & in lpt_fdi_reset_mphy()
240 if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) in lpt_get_iclkip()
403 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); in spll_uses_pch_ssc()
404 u32 ctl = intel_de_read(dev_priv, SPLL_CTL); in spll_uses_pch_ssc()
423 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); in wrpll_uses_pch_ssc()
424 u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id)); in wrpll_uses_pch_ssc()
537 u32 temp = intel_de_read(dev_priv, PCH_DPLL(i)); in ilk_init_pch_refclk()
[all …]
A Dvlv_dsi_pll.c270 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_is_enabled()
284 val = intel_de_read(dev_priv, BXT_DSI_PLL_CTL); in bxt_dsi_pll_is_enabled()
309 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_disable()
361 config->dsi_pll.ctrl = intel_de_read(dev_priv, BXT_DSI_PLL_CTL); in bxt_dsi_get_pclk()
375 temp = intel_de_read(dev_priv, MIPI_CTRL(port)); in vlv_dsi_reset_clocks()
442 tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); in bxt_dsi_program_clocks()
562 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_enable()
585 tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); in bxt_dsi_reset_clocks()
592 tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV1); in bxt_dsi_reset_clocks()
596 tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV2); in bxt_dsi_reset_clocks()
A Dintel_fifo_underrun.c99 if ((intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) in i9xx_check_fifo_underruns()
126 if (old && intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) in i9xx_set_fifo_underrun_reporting()
149 u32 err_int = intel_de_read(dev_priv, GEN7_ERR_INT); in ivb_check_fifo_underruns()
180 intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { in ivb_set_fifo_underrun_reporting()
236 u32 serr_int = intel_de_read(dev_priv, SERR_INT); in cpt_check_pch_fifo_underruns()
269 if (old && intel_de_read(dev_priv, SERR_INT) & in cpt_set_fifo_underrun_reporting()
418 underruns = intel_de_read(dev_priv, ICL_PIPESTATUS(pipe)) & in intel_cpu_fifo_underrun_irq_handler()
A Dintel_tc.c140 pin_mask = intel_de_read(i915, PORT_TX_DFLEXPA1(dig_port->tc_phy_fia)); in intel_tc_port_get_pin_assignment_mask()
193 val = intel_de_read(i915, PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia)); in intel_tc_port_set_fia_lane_count()
247 val = intel_de_read(i915, PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia)); in icl_tc_port_live_status_mask()
261 if (intel_de_read(i915, SDEISR) & isr_bit) in icl_tc_port_live_status_mask()
283 val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); in adl_tc_port_live_status_mask()
289 if (intel_de_read(i915, SDEISR) & isr_bit) in adl_tc_port_live_status_mask()
322 val = intel_de_read(i915, PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia)); in icl_tc_phy_status_complete()
346 val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); in adl_tc_phy_status_complete()
373 val = intel_de_read(i915, PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia)); in icl_tc_phy_take_ownership()
435 val = intel_de_read(i915, DDI_BUF_CTL(port)); in adl_tc_phy_is_owned()
[all …]
A Dintel_display_power.c1141 u32 val = intel_de_read(dev_priv, LCPLL_CTL); in hsw_assert_cdclk()
1201 return intel_de_read(dev_priv, D_COMP_HSW); in hsw_read_dcomp()
1203 return intel_de_read(dev_priv, D_COMP_BDW); in hsw_read_dcomp()
1233 val = intel_de_read(dev_priv, LCPLL_CTL); in hsw_disable_lcpll()
1243 val = intel_de_read(dev_priv, LCPLL_CTL); in hsw_disable_lcpll()
1263 val = intel_de_read(dev_priv, LCPLL_CTL); in hsw_disable_lcpll()
1278 val = intel_de_read(dev_priv, LCPLL_CTL); in hsw_restore_lcpll()
1301 val = intel_de_read(dev_priv, LCPLL_CTL); in hsw_restore_lcpll()
1309 val = intel_de_read(dev_priv, LCPLL_CTL); in hsw_restore_lcpll()
1355 val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D); in hsw_enable_pc8()
[all …]
A Dintel_vrr.c218 return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND; in intel_vrr_is_push_sent()
246 trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder)); in intel_vrr_get_config()
259 crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1; in intel_vrr_get_config()
260 crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1; in intel_vrr_get_config()
261 crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1; in intel_vrr_get_config()
A Dg4x_dp.c143 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe)); in intel_dp_prepare()
258 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p)); in cpt_dp_port_selected()
282 val = intel_de_read(dev_priv, dp_reg); in g4x_dp_port_enabled()
349 tmp = intel_de_read(dev_priv, intel_dp->output_reg); in intel_dp_get_config()
354 u32 trans_dp = intel_de_read(dev_priv, in intel_dp_get_config()
415 (intel_de_read(dev_priv, intel_dp->output_reg) & in intel_dp_link_down()
645 u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg); in intel_enable_dp()
1177 return intel_de_read(dev_priv, SDEISR) & bit; in ibx_digital_port_connected()
1200 return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit; in g4x_digital_port_connected()
1223 return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit; in gm45_digital_port_connected()
[all …]
A Dintel_tv.c914 u32 tmp = intel_de_read(dev_priv, TV_CTL); in intel_tv_get_hw_state()
1102 tv_ctl = intel_de_read(dev_priv, TV_CTL); in intel_tv_get_config()
1103 hctl1 = intel_de_read(dev_priv, TV_H_CTL_1); in intel_tv_get_config()
1104 hctl3 = intel_de_read(dev_priv, TV_H_CTL_3); in intel_tv_get_config()
1105 vctl1 = intel_de_read(dev_priv, TV_V_CTL_1); in intel_tv_get_config()
1106 vctl2 = intel_de_read(dev_priv, TV_V_CTL_2); in intel_tv_get_config()
1141 tmp = intel_de_read(dev_priv, TV_WIN_POS); in intel_tv_get_config()
1145 tmp = intel_de_read(dev_priv, TV_WIN_SIZE); in intel_tv_get_config()
1453 tv_ctl = intel_de_read(dev_priv, TV_CTL); in intel_tv_pre_enable()
1637 tv_dac = intel_de_read(dev_priv, TV_DAC); in intel_tv_detect_type()
[all …]
A Dintel_hdmi.c280 u32 val = intel_de_read(dev_priv, reg); in ibx_write_infoframe()
337 u32 val = intel_de_read(dev_priv, reg); in ibx_infoframes_enabled()
359 u32 val = intel_de_read(dev_priv, reg); in cpt_write_infoframe()
437 u32 val = intel_de_read(dev_priv, reg); in vlv_write_infoframe()
486 *data++ = intel_de_read(dev_priv, in vlv_read_infoframe()
559 *data++ = intel_de_read(dev_priv, in hsw_read_infoframe()
567 u32 val = intel_de_read(dev_priv, in hsw_infoframes_enabled()
871 u32 val = intel_de_read(dev_priv, reg); in g4x_set_infoframes()
1056 u32 val = intel_de_read(dev_priv, reg); in ibx_set_infoframes()
1114 u32 val = intel_de_read(dev_priv, reg); in cpt_set_infoframes()
[all …]
A Dintel_display.c490 intel_de_read(dev_priv, dpll_reg) & port_mask, in vlv_wait_port_ready()
534 val = intel_de_read(dev_priv, reg); in intel_enable_transcoder()
573 val = intel_de_read(dev_priv, reg); in intel_disable_transcoder()
1806 val = intel_de_read(dev_priv, reg); in hsw_set_frame_start_delay()
2326 intel_de_read(dev_priv, PFIT_CONTROL)); in i9xx_pfit_disable()
3063 tmp = intel_de_read(dev_priv, PFIT_CONTROL); in i9xx_get_pfit_config()
3078 intel_de_read(dev_priv, PFIT_PGM_RATIOS); in i9xx_get_pfit_config()
4041 u32 tmp = intel_de_read(dev_priv, in hsw_get_pipe_config()
4092 intel_de_read(dev_priv, in hsw_get_pipe_config()
4418 u32 lvds = intel_de_read(dev_priv, LVDS); in i9xx_crtc_clock_get()
[all …]
A Dintel_ddi.c755 tmp = intel_de_read(dev_priv, in intel_ddi_get_encoder_pipes()
796 tmp = intel_de_read(dev_priv, in intel_ddi_get_encoder_pipes()
1479 return !(intel_de_read(i915, reg) & clk_off); in _icl_ddi_is_clock_enabled()
1726 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); in jsl_ddi_tc_is_clock_enabled()
1779 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); in icl_ddi_tc_is_clock_enabled()
1784 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); in icl_ddi_tc_is_clock_enabled()
1797 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); in icl_ddi_tc_get_pll()
1895 tmp = intel_de_read(i915, DPLL_CTRL2); in skl_ddi_get_pll()
2665 val = intel_de_read(dev_priv, in intel_ddi_post_disable_dp()
2909 val = intel_de_read(dev_priv, reg); in intel_enable_ddi_hdmi()
[all …]
A Dintel_dmc.c299 event_ctl = intel_de_read(i915, ctl_reg); in disable_flip_queue_event()
300 event_htp = intel_de_read(i915, htp_reg); in disable_flip_queue_event()
508 … !intel_de_read(i915, DMC_PROGRAM(i915->display.dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), in assert_dmc_loaded()
510 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE), in assert_dmc_loaded()
512 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL), in assert_dmc_loaded()
1120 intel_de_read(i915, dc3co_reg)); in intel_dmc_debugfs_status_show()
1128 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg)); in intel_dmc_debugfs_status_show()
1131 intel_de_read(i915, dc6_reg)); in intel_dmc_debugfs_status_show()
1135 intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); in intel_dmc_debugfs_status_show()
1137 intel_de_read(i915, DMC_SSP_BASE)); in intel_dmc_debugfs_status_show()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/i915/
A Di915_suspend.c43 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
44 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
47 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); in intel_save_swf()
50 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
53 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
54 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
57 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); in intel_save_swf()
95 dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB); in i915_save_display()

Completed in 102 milliseconds

123