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Searched refs:intel_de_write_fw (Results 1 – 13 of 13) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/i915/display/
A Dintel_sprite.c169 intel_de_write_fw(dev_priv, SPCSCC01(plane_id), in chv_sprite_update_csc()
171 intel_de_write_fw(dev_priv, SPCSCC23(plane_id), in chv_sprite_update_csc()
173 intel_de_write_fw(dev_priv, SPCSCC45(plane_id), in chv_sprite_update_csc()
175 intel_de_write_fw(dev_priv, SPCSCC67(plane_id), in chv_sprite_update_csc()
859 intel_de_write_fw(dev_priv, SPRSTRIDE(pipe), in ivb_sprite_update_noarm()
861 intel_de_write_fw(dev_priv, SPRPOS(pipe), in ivb_sprite_update_noarm()
863 intel_de_write_fw(dev_priv, SPRSIZE(pipe), in ivb_sprite_update_noarm()
910 intel_de_write_fw(dev_priv, SPRSURF(pipe), in ivb_sprite_update_arm()
1188 intel_de_write_fw(dev_priv, DVSPOS(pipe), in g4x_sprite_update_noarm()
1190 intel_de_write_fw(dev_priv, DVSSIZE(pipe), in g4x_sprite_update_noarm()
[all …]
A Dskl_scaler.c476 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl); in skl_pfit_enable()
478 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id), in skl_pfit_enable()
480 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id), in skl_pfit_enable()
482 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id), in skl_pfit_enable()
484 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id), in skl_pfit_enable()
540 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id), in skl_program_plane_scaler()
542 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id), in skl_program_plane_scaler()
544 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id), in skl_program_plane_scaler()
546 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id), in skl_program_plane_scaler()
555 intel_de_write_fw(dev_priv, SKL_PS_CTRL(crtc->pipe, id), 0); in skl_detach_scaler()
[all …]
A Dskl_universal_plane.c582 intel_de_write_fw(dev_priv, in icl_program_input_csc()
584 intel_de_write_fw(dev_priv, in icl_program_input_csc()
586 intel_de_write_fw(dev_priv, in icl_program_input_csc()
628 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); in skl_plane_disable_arm()
1127 intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id), in skl_plane_update_noarm()
1129 intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id), in skl_plane_update_noarm()
1187 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), in skl_plane_update_arm()
1221 intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id), in icl_plane_update_noarm()
1223 intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id), in icl_plane_update_noarm()
1296 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), in icl_plane_update_arm()
[all …]
A Dintel_gmbus.c408 intel_de_write_fw(i915, GMBUS4(i915), 0); in gmbus_wait()
434 intel_de_write_fw(i915, GMBUS4(i915), 0); in gmbus_wait_idle()
465 intel_de_write_fw(i915, GMBUS0(i915), in gmbus_xfer_read_chunk()
469 intel_de_write_fw(i915, GMBUS1(i915), in gmbus_xfer_read_chunk()
547 intel_de_write_fw(i915, GMBUS3(i915), val); in gmbus_xfer_write_chunk()
548 intel_de_write_fw(i915, GMBUS1(i915), in gmbus_xfer_write_chunk()
633 intel_de_write_fw(i915, GMBUS5(i915), 0); in gmbus_index_xfer()
694 intel_de_write_fw(i915, GMBUS0(i915), 0); in do_gmbus_xfer()
725 intel_de_write_fw(i915, GMBUS1(i915), 0); in do_gmbus_xfer()
726 intel_de_write_fw(i915, GMBUS0(i915), 0); in do_gmbus_xfer()
[all …]
A Dintel_color.c198 intel_de_write_fw(i915, PIPE_CSC_COEFF_RY_GY(pipe), in ilk_update_pipe_csc()
202 intel_de_write_fw(i915, PIPE_CSC_COEFF_RU_GU(pipe), in ilk_update_pipe_csc()
206 intel_de_write_fw(i915, PIPE_CSC_COEFF_RV_GV(pipe), in ilk_update_pipe_csc()
211 intel_de_write_fw(i915, PIPE_CSC_POSTOFF_HI(pipe), in ilk_update_pipe_csc()
213 intel_de_write_fw(i915, PIPE_CSC_POSTOFF_ME(pipe), in ilk_update_pipe_csc()
215 intel_de_write_fw(i915, PIPE_CSC_POSTOFF_LO(pipe), in ilk_update_pipe_csc()
763 intel_de_write_fw(dev_priv, PALETTE(pipe, i), in i9xx_load_lut_8()
847 intel_de_write_fw(i915, reg, val); in ilk_lut_write()
2862 intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), in bdw_read_lut_10()
2864 intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), in bdw_read_lut_10()
[all …]
A Di9xx_plane.c424 intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane), in i9xx_plane_update_noarm()
438 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane), in i9xx_plane_update_noarm()
440 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), in i9xx_plane_update_noarm()
470 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane), in i9xx_plane_update_arm()
472 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), in i9xx_plane_update_arm()
478 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane), in i9xx_plane_update_arm()
481 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane), in i9xx_plane_update_arm()
483 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane), in i9xx_plane_update_arm()
495 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in i9xx_plane_update_arm()
498 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), in i9xx_plane_update_arm()
[all …]
A Dintel_cursor.c284 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0); in i845_cursor_update_arm()
285 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); in i845_cursor_update_arm()
286 intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size); in i845_cursor_update_arm()
287 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); in i845_cursor_update_arm()
294 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); in i845_cursor_update_arm()
543 intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe), in i9xx_cursor_update_arm()
545 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl); in i9xx_cursor_update_arm()
546 intel_de_write_fw(dev_priv, CURPOS(pipe), pos); in i9xx_cursor_update_arm()
547 intel_de_write_fw(dev_priv, CURBASE(pipe), base); in i9xx_cursor_update_arm()
553 intel_de_write_fw(dev_priv, CURPOS(pipe), pos); in i9xx_cursor_update_arm()
[all …]
A Dintel_de.h108 intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val) in intel_de_write_fw() function
A Dintel_psr.c1559 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0); in intel_psr2_disable_plane_sel_fetch()
1577 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), in intel_psr2_program_plane_sel_fetch()
1586 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); in intel_psr2_program_plane_sel_fetch()
1601 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), in intel_psr2_program_plane_sel_fetch()
1607 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); in intel_psr2_program_plane_sel_fetch()
1609 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), in intel_psr2_program_plane_sel_fetch()
A Dintel_fbc.c326 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), in i8xx_fbc_nuke()
360 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in i965_fbc_nuke()
A Dintel_dmc.c459 intel_de_write_fw(dev_priv, in intel_dmc_load_program()
A Dintel_display.c1082 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | in ilk_pfit_enable()
1085 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | in ilk_pfit_enable()
1087 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y); in ilk_pfit_enable()
1088 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height); in ilk_pfit_enable()
1961 intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); in ilk_pfit_disable()
1962 intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); in ilk_pfit_disable()
1963 intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); in ilk_pfit_disable()
A Dskl_watermark.c2224 intel_de_write_fw(i915, reg, in skl_ddb_entry_write()
2228 intel_de_write_fw(i915, reg, 0); in skl_ddb_entry_write()
2244 intel_de_write_fw(i915, reg, val); in skl_write_wm_level()

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