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Searched refs:invalidate (Results 1 – 25 of 138) sorted by relevance

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/linux-6.3-rc2/arch/arm/mm/
A Dcache-fa.S45 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
66 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
68 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
69 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
91 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
92 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
97 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
128 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
133 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
154 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
A Dcache-v6.S42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
66 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
68 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
73 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
145 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
150 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
[all …]
A Dproc-arm926.S69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
109 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
132 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
159 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
162 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
205 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
229 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
296 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
A Dproc-arm925.S109 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
143 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
166 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
175 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
196 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
199 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
242 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
266 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
333 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
395 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
[all …]
A Dproc-mohawk.S62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
116 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
139 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
142 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
178 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
202 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
318 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
378 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches
[all …]
A Dproc-arm920.S77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
108 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
194 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
218 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
241 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
337 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
351 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
[all …]
A Dproc-arm922.S79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
82 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
110 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
140 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
162 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
196 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
220 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
243 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
341 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
355 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
[all …]
A Dcache-v4wt.S48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
70 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
71 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
89 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
91 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
122 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
140 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
157 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
A Dproc-fa526.S58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
61 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
104 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
106 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
108 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
109 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
113 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
137 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
140 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
142 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
[all …]
A Dproc-arm1022.S85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
151 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
216 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
267 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
381 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
385 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
408 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
[all …]
A Dproc-arm1026.S85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
146 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
175 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
210 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
261 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
370 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
374 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
397 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
[all …]
A Dproc-arm946.S83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
137 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
138 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
140 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
141 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
184 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
209 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
277 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
328 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
A Dproc-arm1020e.S85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
181 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
216 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
267 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
388 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
392 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
415 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
[all …]
A Dtlb-v7.S49 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
51 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
53 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
78 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
80 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
82 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
A Dtlb-v6.S48 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
50 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
52 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
77 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
78 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
80 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
A Dproc-arm1020.S85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
153 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
184 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
222 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
278 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
404 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
408 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
433 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
[all …]
A Dproc-feroceon.S91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
157 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
178 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
181 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
217 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
242 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
256 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
280 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
A Dproc-xsc3.S68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
118 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
196 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
197 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
202 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
272 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
367 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
433 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
[all …]
A Dcache-v4wb.S59 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
78 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
112 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
118 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
165 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
170 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
192 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
A Dtlb-v4wb.S38 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
41 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
61 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
62 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
A Dcache-v7.S86 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
165 mcr p15, 0, r5, c7, c14, 2 @ clean & invalidate by set/way
201 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
217 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
302 USER( mcr p15, 0, r12, c7, c5, 1 ) @ invalidate I line
307 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable
308 ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB
373 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
378 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line
381 mcrlo p15, 0, r0, c7, c6, 1 @ invalidate D / U line
[all …]
A Dtlb-v4wbi.S40 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
41 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
52 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
53 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
A Dproc-sa1100.S73 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
76 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
147 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
149 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
187 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
201 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
204 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
A Dproc-sa110.S65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
68 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
138 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
162 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
165 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
/linux-6.3-rc2/drivers/net/ethernet/mellanox/mlx5/core/lib/
A Dhv_vhca.c36 void (*invalidate)(struct mlx5_hv_vhca_agent *agent, member
83 if (!agent || !agent->invalidate) in mlx5_hv_vhca_invalidate_work()
89 agent->invalidate(agent, hwork->block_mask); in mlx5_hv_vhca_invalidate_work()
256 void (*invalidate)(struct mlx5_hv_vhca_agent*, in mlx5_hv_vhca_agent_create()
284 agent->invalidate = invalidate; in mlx5_hv_vhca_agent_create()

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