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/linux-6.3-rc2/drivers/phy/freescale/
A Dphy-fsl-lynx-28g.c46 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) argument
55 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) argument
61 #define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24) argument
70 #define LYNX_28G_LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30) argument
98 #define LYNX_28G_LNaPSS(lane) (0x1000 + (lane) * 0x4) argument
103 #define LYNX_28G_SGMIIaCR1(lane) (0x1804 + (lane) * 0x10) argument
148 lynx_28g_rmw((lane)->priv, LYNX_28G_##reg(lane->id), \
151 ioread32((lane)->priv->base + LYNX_28G_##reg((lane)->id))
508 lane = &priv->lane[i]; in lynx_28g_cdr_lock_check()
577 struct lynx_28g_lane *lane = &priv->lane[i]; in lynx_28g_probe() local
[all …]
/linux-6.3-rc2/drivers/phy/marvell/
A Dphy-mvebu-a3700-comphy.c521 lane->id, lane->mode, old, new); in mvebu_a3700_comphy_set_phy_selector()
526 lane->mode); in mvebu_a3700_comphy_set_phy_selector()
671 lane->submode, lane->id); in mvebu_a3700_comphy_ethernet_power_on()
779 lane->id); in mvebu_a3700_comphy_ethernet_power_on()
804 lane->id); in mvebu_a3700_comphy_ethernet_power_on()
813 lane->id); in mvebu_a3700_comphy_ethernet_power_on()
1121 if (mvebu_a3700_comphy_modes[i].lane == lane && in mvebu_a3700_comphy_check_mode()
1145 (lane->mode != mode || lane->submode != submode)) in mvebu_a3700_comphy_set_mode()
1159 if (!mvebu_a3700_comphy_check_mode(lane->id, lane->mode, in mvebu_a3700_comphy_power_on()
1170 dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id); in mvebu_a3700_comphy_power_on()
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A Dphy-mvebu-cp110-comphy.c181 unsigned lane; member
308 if (conf->lane == lane && in mvebu_comphy_get_mode()
380 lane->id); in mvebu_comphy_ethernet_init_reset()
401 lane->id); in mvebu_comphy_ethernet_init_reset()
728 mux = mvebu_comphy_get_mux(lane->id, lane->port, in mvebu_comphy_power_on_legacy()
729 lane->mode, lane->submode); in mvebu_comphy_power_on_legacy()
773 fw_mode = mvebu_comphy_get_fw_mode(lane->id, lane->port, in mvebu_comphy_power_on()
774 lane->mode, lane->submode); in mvebu_comphy_power_on()
784 lane->id); in mvebu_comphy_power_on()
789 lane->id); in mvebu_comphy_power_on()
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A Dphy-armada38x-comphy.c66 conf |= BIT(lane->port); in a38x_set_conf()
68 conf &= ~BIT(lane->port); in a38x_set_conf()
102 dev_err(lane->priv->dev, in a38x_comphy_poll()
135 a38x_set_conf(lane, false); in a38x_comphy_set_mode()
146 a38x_set_conf(lane, true); in a38x_comphy_set_mode()
171 if (lane->port >= 0) in a38x_comphy_xlate()
174 lane->port = args->args[0]; in a38x_comphy_xlate()
179 if (!gbe_mux[lane->n][lane->port] || in a38x_comphy_xlate()
180 val != gbe_mux[lane->n][lane->port]) { in a38x_comphy_xlate()
181 dev_warn(lane->priv->dev, in a38x_comphy_xlate()
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/linux-6.3-rc2/drivers/net/dsa/b53/
A Db53_serdes.c44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
47 WARN_ON(lane > 1); in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
74 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_config() local
92 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_an_restart() local
106 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_get_state() local
173 switch (lane) { in b53_serdes_phylink_get_caps()
200 if (lane == B53_INVALID_LANE || lane >= B53_N_PCS || in b53_serdes_phylink_mac_select_pcs()
201 !dev->pcs[lane].dev) in b53_serdes_phylink_mac_select_pcs()
238 pcs = &dev->pcs[lane]; in b53_serdes_init()
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/linux-6.3-rc2/drivers/net/dsa/mv88e6xxx/
A Dserdes.c271 return lane; in mv88e6352_serdes_get_lane()
382 int lane) in mv88e6352_serdes_irq_status() argument
461 return lane; in mv88e6341_serdes_get_lane()
559 int lane) in mv88e6097_serdes_irq_status() argument
593 return lane; in mv88e6390_serdes_get_lane()
668 return lane; in mv88e6390x_serdes_get_lane()
687 lane = port; in mv88e6393x_serdes_get_lane()
689 return lane; in mv88e6393x_serdes_get_lane()
801 int lane; in mv88e6390_serdes_get_stats() local
805 if (lane < 0) in mv88e6390_serdes_get_stats()
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A Dserdes.h113 int lane, unsigned int mode,
129 int lane);
131 int lane);
156 int lane, bool enable);
158 int lane);
160 int lane);
162 int lane);
164 int lane);
195 int port, int lane) in mv88e6xxx_serdes_power_up() argument
204 int port, int lane) in mv88e6xxx_serdes_power_down() argument
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/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/link/protocols/
A Dlink_dp_training_fixed_vs_pe_retimer.c55 uint8_t lane; in dp_fixed_vs_pe_read_lane_adjust() local
86 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_fixed_vs_pe_read_lane_adjust()
104 uint8_t lane = 0; in dp_fixed_vs_pe_set_retimer_lane_settings() local
111 for (lane = 0; lane < lane_count; lane++) { in dp_fixed_vs_pe_set_retimer_lane_settings()
113 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET << (2 * lane); in dp_fixed_vs_pe_set_retimer_lane_settings()
115 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET << (2 * lane); in dp_fixed_vs_pe_set_retimer_lane_settings()
142 uint8_t lane = 0; in perform_fixed_vs_pe_nontransparent_training_sequence() local
204 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in perform_fixed_vs_pe_nontransparent_training_sequence()
241 uint8_t lane = 0; in dp_perform_fixed_vs_pe_training_sequence() local
403 for (lane = 0; lane < lane_count; lane++) { in dp_perform_fixed_vs_pe_training_sequence()
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A Dlink_dp_training.c332 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in maximize_lane_settings()
346 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_hw_to_dpcd_lane_settings()
451 for (lane = 0; lane < in dp_is_max_vs_reached()
468 for (lane = 0; lane < (uint32_t)(ln_count); lane++) { in dp_is_cr_done()
481 for (lane = 0; lane < (uint32_t)(ln_count); lane++) in dp_is_ch_eq_done()
492 for (lane = 0; lane < (uint32_t)(ln_count); lane++) in dp_is_symbol_locked()
577 for (lane = 0; lane < in dp_get_lane_status_and_lane_adjust()
639 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in override_lane_settings()
695 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in override_training_settings()
805 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_decide_lane_settings()
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/linux-6.3-rc2/drivers/phy/
A Dphy-xgene.c688 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
690 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
698 serdes_rd(ctx, lane, reg, &val); in serdes_setbits()
700 serdes_wr(ctx, lane, reg, val); in serdes_setbits()
943 int lane; in xgene_phy_sata_cfg_lanes() local
945 for (lane = 0; lane < MAX_LANE; lane++) { in xgene_phy_sata_cfg_lanes()
960 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
988 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
991 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
994 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
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/linux-6.3-rc2/drivers/phy/tegra/
A Dxusb.c143 lane->pad->ops->remove(lane); in tegra_xusb_lane_destroy()
331 lane->pad->ops->iddq_enable(lane); in tegra_xusb_lane_program()
340 lane->pad->ops->iddq_disable(lane); in tegra_xusb_lane_program()
394 const char *func = lane->soc->funcs[lane->function]; in tegra_xusb_lane_check()
412 hit = lane; in tegra_xusb_find_lane()
444 match = lane; in tegra_xusb_port_find_lane()
1394 return lane->pad->ops->enable_phy_sleepwalk(lane, speed); in tegra_xusb_padctl_enable_phy_sleepwalk()
1405 return lane->pad->ops->disable_phy_sleepwalk(lane); in tegra_xusb_padctl_disable_phy_sleepwalk()
1416 return lane->pad->ops->enable_phy_wake(lane); in tegra_xusb_padctl_enable_phy_wake()
1427 return lane->pad->ops->disable_phy_wake(lane); in tegra_xusb_padctl_disable_phy_wake()
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A Dxusb.h63 to_usb3_lane(struct tegra_xusb_lane *lane) in to_usb3_lane() argument
76 to_usb2_lane(struct tegra_xusb_lane *lane) in to_usb2_lane() argument
86 to_ulpi_lane(struct tegra_xusb_lane *lane) in to_ulpi_lane() argument
105 to_hsic_lane(struct tegra_xusb_lane *lane) in to_hsic_lane() argument
115 to_pcie_lane(struct tegra_xusb_lane *lane) in to_pcie_lane() argument
125 to_sata_lane(struct tegra_xusb_lane *lane) in to_sata_lane() argument
134 void (*remove)(struct tegra_xusb_lane *lane);
135 void (*iddq_enable)(struct tegra_xusb_lane *lane);
136 void (*iddq_disable)(struct tegra_xusb_lane *lane);
139 int (*enable_phy_wake)(struct tegra_xusb_lane *lane);
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A Dxusb-tegra210.c455 lane->pad->soc->lanes[lane->index].name, map->port); in tegra210_usb3_lane_map()
716 if (IS_ERR(lane)) in tegra210_sata_uphy_enable()
1699 struct tegra_xusb_lane *lane; in tegra210_usb3_set_lfps_detect() local
1706 lane = port->lane; in tegra210_usb3_set_lfps_detect()
1919 lane->index); in tegra210_usb2_phy_set_mode()
2123 lane->index); in tegra210_usb2_phy_power_off()
2567 if (!lane || !lane->pad || !lane->pad->padctl) in tegra210_lane_to_usb3_port()
3089 struct tegra_xusb_lane *lane; in tegra210_utmi_port_reset() local
3092 lane = phy_get_drvdata(phy); in tegra210_utmi_port_reset()
3093 padctl = lane->pad->padctl; in tegra210_utmi_port_reset()
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A Dxusb-tegra124.c292 struct tegra_xusb_lane *lane; in tegra124_usb3_save_context() local
300 lane = port->base.lane; in tegra124_usb3_save_context()
302 if (lane->pad == padctl->pcie) in tegra124_usb3_save_context()
486 unsigned int index = lane->index; in tegra124_usb2_phy_power_on()
578 lane->index); in tegra124_usb2_phy_power_off()
869 unsigned int index = lane->index; in tegra124_hsic_phy_power_on()
938 unsigned int index = lane->index; in tegra124_hsic_phy_power_off()
1480 struct tegra_xusb_lane *lane = usb3->base.lane; in tegra124_usb3_port_enable() local
1542 if (lane->pad == padctl->pcie) in tegra124_usb3_port_enable()
1554 if (lane->pad == padctl->pcie) in tegra124_usb3_port_enable()
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A Dxusb-tegra186.c325 unsigned int index = lane->index; in tegra186_utmi_enable_phy_sleepwalk()
469 unsigned int index = lane->index; in tegra186_utmi_disable_phy_sleepwalk()
509 unsigned int index = lane->index; in tegra186_utmi_enable_phy_wake()
534 unsigned int index = lane->index; in tegra186_utmi_disable_phy_wake()
559 unsigned int index = lane->index; in tegra186_utmi_phy_remote_wake_detected()
683 unsigned int index = lane->index; in tegra186_utmi_pad_power_on()
714 unsigned int index = lane->index; in tegra186_utmi_pad_power_down()
793 lane->index); in tegra186_utmi_phy_set_mode()
833 unsigned int index = lane->index; in tegra186_utmi_phy_power_on()
909 unsigned int index = lane->index; in tegra186_utmi_phy_init()
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/linux-6.3-rc2/sound/soc/tegra/
A Dtegra186_asrc.c117 asrc->lane[id].int_part); in tegra186_asrc_runtime_resume()
122 asrc->lane[id].frac_part); in tegra186_asrc_runtime_resume()
231 asrc->lane[id].int_part); in tegra186_asrc_out_hw_params()
234 asrc->lane[id].frac_part); in tegra186_asrc_out_hw_params()
269 asrc->lane[id].ratio_source, in tegra186_asrc_put_ratio_source()
286 &asrc->lane[id].int_part); in tegra186_asrc_get_ratio_int()
334 &asrc->lane[id].frac_part); in tegra186_asrc_get_ratio_frac()
997 asrc->lane[i].int_part = 1; in tegra186_asrc_platform_probe()
998 asrc->lane[i].frac_part = 0; in tegra186_asrc_platform_probe()
1000 asrc->lane[i].input_thresh = in tegra186_asrc_platform_probe()
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/linux-6.3-rc2/drivers/gpu/drm/bridge/analogix/
A Danalogix_dp_core.c269 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
290 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
316 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
341 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_clock_recovery_ok()
358 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_channel_eq_ok()
450 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_get_adjust_training_lane()
499 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_process_clock_recovery()
527 for (lane = 0; lane < lane_count; lane++) in analogix_dp_process_clock_recovery()
529 dp->link_train.training_lane[lane], lane); in analogix_dp_process_clock_recovery()
601 for (lane = 0; lane < lane_count; lane++) in analogix_dp_process_equalizer_training()
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/linux-6.3-rc2/drivers/gpu/drm/i915/display/
A Dintel_dp_link_training.c322 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_tx_ffe_preset()
325 for (lane = 0; lane < crtc_state->lane_count; lane++) in intel_dp_get_lane_adjust_tx_ffe_preset()
345 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_vswing_preemph()
350 for (lane = 0; lane < crtc_state->lane_count; lane++) { in intel_dp_get_lane_adjust_vswing_preemph()
373 int lane) in intel_dp_get_lane_adjust_train() argument
414 int lane; in intel_dp_get_adjust_train() local
434 for (lane = 0; lane < 4; lane++) in intel_dp_get_adjust_train()
623 int lane; in intel_dp_link_max_vswing_reached() local
625 for (lane = 0; lane < crtc_state->lane_count; lane++) { in intel_dp_link_max_vswing_reached()
714 int lane; in intel_dp_adjust_request_changed() local
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/linux-6.3-rc2/drivers/phy/rockchip/
A Dphy-rockchip-typec.c507 writel(0x7799, tcphy->base + TX_PSC_A0(lane)); in tcphy_tx_usb3_cfg_lane()
508 writel(0x7798, tcphy->base + TX_PSC_A1(lane)); in tcphy_tx_usb3_cfg_lane()
509 writel(0x5098, tcphy->base + TX_PSC_A2(lane)); in tcphy_tx_usb3_cfg_lane()
510 writel(0x5098, tcphy->base + TX_PSC_A3(lane)); in tcphy_tx_usb3_cfg_lane()
517 writel(0xa6fd, tcphy->base + RX_PSC_A0(lane)); in tcphy_rx_usb3_cfg_lane()
518 writel(0xa6fd, tcphy->base + RX_PSC_A1(lane)); in tcphy_rx_usb3_cfg_lane()
519 writel(0xa410, tcphy->base + RX_PSC_A2(lane)); in tcphy_rx_usb3_cfg_lane()
520 writel(0x2410, tcphy->base + RX_PSC_A3(lane)); in tcphy_rx_usb3_cfg_lane()
534 writel(0x6799, tcphy->base + TX_PSC_A0(lane)); in tcphy_dp_cfg_lane()
536 writel(0x98, tcphy->base + TX_PSC_A2(lane)); in tcphy_dp_cfg_lane()
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/linux-6.3-rc2/Documentation/devicetree/bindings/media/i2c/
A Dst,st-mipid02.yaml17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
18 second input port is a single lane 800Mbps. Both ports support clock
19 and data lane polarity swap. First port also supports data lane swap.
65 Single-lane operation shall be <1> or <2> .
66 Dual-lane operation shall be <1 2> or <2 1> .
70 lane-polarities:
72 Any lane can be inverted or not.
91 Single-lane operation shall be <1> or <2> .
94 lane-polarities:
96 Any lane can be inverted or not.
/linux-6.3-rc2/drivers/phy/mediatek/
A Dphy-mtk-pcie.c81 unsigned int lane) in mtk_pcie_efuse_set_lane() argument
83 struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_set_lane()
90 lane * PEXTP_ANA_LANE_OFFSET; in mtk_pcie_efuse_set_lane()
134 unsigned int lane) in mtk_pcie_efuse_read_for_lane() argument
136 struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_read_for_lane()
141 snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane); in mtk_pcie_efuse_read_for_lane()
146 snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_nmos", lane); in mtk_pcie_efuse_read_for_lane()
151 snprintf(efuse_id, sizeof(efuse_id), "rx_ln%d", lane); in mtk_pcie_efuse_read_for_lane()
159 lane); in mtk_pcie_efuse_read_for_lane()
/linux-6.3-rc2/arch/mips/cavium-octeon/executive/
A Dcvmx-helper-errata.c51 int lane; in __cvmx_helper_errata_qlm_disable_2nd_order_cdr() local
54 for (lane = 0; lane < 4; lane++) { in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
/linux-6.3-rc2/drivers/net/ethernet/ti/
A Dnetcp_xgbepcsr.c148 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument
156 (0x200 * lane), in netcp_xgbe_serdes_lane_config()
162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config()
166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config()
182 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_enable() argument
185 writel(0xe0e9e038, serdes_regs + 0x1fe0 + (4 * lane)); in netcp_xgbe_serdes_lane_enable()
283 void __iomem *sig_detect_reg, int lane) in netcp_xgbe_serdes_reset_cdr() argument
289 serdes_regs, lane + 1, 5); in netcp_xgbe_serdes_reset_cdr()
298 tbus = netcp_xgbe_serdes_read_select_tbus(serdes_regs, lane + in netcp_xgbe_serdes_reset_cdr()
430 int lane, int cm, int c1, int c2) in netcp_xgbe_serdes_setup_cm_c1_c2() argument
[all …]
/linux-6.3-rc2/Documentation/devicetree/bindings/media/
A Dvideo-interfaces.yaml164 # Assume up to 9 physical lane indices
167 An array of physical data lane indexes. Position of an entry determines
169 lane, e.g. for 2-lane MIPI CSI-2 bus we could have "data-lanes = <1 2>;",
170 assuming the clock lane is on hardware lane 0. If the hardware does not
173 lane. This property is valid for serial busses only (e.g. MIPI CSI-2).
177 # Assume up to 9 physical lane indices
180 Physical clock lane index. Position of an entry determines the logical
181 lane number, while the value of an entry indicates physical lane, e.g. for
183 clock lane on hardware lane 0. This property is valid for serial busses
198 lane-polarities:
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/linux-6.3-rc2/drivers/pinctrl/tegra/
A Dpinctrl-tegra-xusb.c306 lane = &padctl->soc->lanes[group]; in tegra_xusb_padctl_pinmux_set()
309 if (lane->funcs[i] == function) in tegra_xusb_padctl_pinmux_set()
312 if (i >= lane->num_funcs) in tegra_xusb_padctl_pinmux_set()
316 value &= ~(lane->mask << lane->shift); in tegra_xusb_padctl_pinmux_set()
317 value |= i << lane->shift; in tegra_xusb_padctl_pinmux_set()
340 lane = &padctl->soc->lanes[group]; in tegra_xusb_padctl_pinconf_group_get()
345 if (lane->iddq == 0) in tegra_xusb_padctl_pinconf_group_get()
350 if (value & BIT(lane->iddq)) in tegra_xusb_padctl_pinconf_group_get()
388 if (lane->iddq == 0) in tegra_xusb_padctl_pinconf_group_set()
394 regval &= ~BIT(lane->iddq); in tegra_xusb_padctl_pinconf_group_set()
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