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/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_hubp.h33 #define HUBP_MASK_SH_LIST_DCN31(mask_sh)\ argument
41 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
42 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
46 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
48 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\
49 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_SOFT_RESET, mask_sh),\
50 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
53 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PKRS, mask_sh),\
54 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
177 HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
[all …]
A Ddcn31_optc.h120 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
126 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
133 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
137 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
169 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
192 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
193 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
194 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
206 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
208 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
[all …]
A Ddcn31_hubbub.h58 #define HUBBUB_MASK_SH_LIST_DCN31(mask_sh)\ argument
59 HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
60 HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
64 HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
65 HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
66 HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
67 HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \
68 HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh),\
95 HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE, mask_sh),\
97 HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE, mask_sh),\
[all …]
A Ddcn31_dio_link_encoder.h42 #define LINK_ENCODER_MASK_SH_LIST_DCN31(mask_sh) \ argument
43 LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh),\
44 LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\
45 LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\
46 LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\
47 LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
62 LE_SF(DIO_LINKA_CNTL, ENC_TYPE_SEL, mask_sh),\
63 LE_SF(DIO_LINKA_CNTL, HPO_DP_ENC_SEL, mask_sh),\
64 LE_SF(DIO_LINKA_CNTL, HPO_HDMI_ENC_SEL, mask_sh)
96 #define DPCS_DCN31_MASK_SH_LIST(mask_sh)\ argument
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_hubp.h37 #define HUBP_MASK_SH_LIST_DCN30_BASE(mask_sh)\ argument
38 HUBP_MASK_SH_LIST_DCN21_COMMON(mask_sh),\
47 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PKRS, mask_sh)
50 #define HUBP_MASK_SH_LIST_DCN30(mask_sh)\ argument
58 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
63 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
64 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\
65 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\
69 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PKRS, mask_sh),\
193 HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
[all …]
A Ddcn30_mmhubbub.h135 #define MCIF_WB_COMMON_MASK_SH_LIST_DCN3_0(mask_sh) \ argument
230 SF(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
267 #define MCIF_WB_COMMON_MASK_SH_LIST_DCN30(mask_sh) \ argument
289 SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
296 SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
304 SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
311 SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
319 SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
326 SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
334 SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\
[all …]
A Ddcn30_optc.h114 #define DCN30_VTOTAL_REGS_SF(mask_sh) argument
132 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
138 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
145 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
149 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
168 DCN30_VTOTAL_REGS_SF(mask_sh)\
183 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
212 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
213 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
214 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
[all …]
A Ddcn30_dio_stream_encoder.h115 #define SE_COMMON_MASK_SH_LIST_DCN30(mask_sh)\ argument
130 SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
149 SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
150 SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
151 SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\
157 SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
159 SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
162 SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
198 SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
211 SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_dpp.h186 #define TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh)\ argument
209 #define TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh)\ argument
210 TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \
368 TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \
369 TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_SIZE, mask_sh), \
371 TF_SF(CM0_CM_3DLUT_DATA, CM_3DLUT_DATA0, mask_sh), \
545 #define TF_REG_LIST_SH_MASK_DCN20(mask_sh)\ argument
546 TF_REG_LIST_SH_MASK_DCN(mask_sh), \
547 TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh), \
548 TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh), \
[all …]
A Ddcn20_link_encoder.h35 #define UNIPHY_MASK_SH_LIST(mask_sh)\ argument
43 #define DPCS_MASK_SH_LIST(mask_sh)\ argument
152 #define DPCS_DCN2_MASK_SH_LIST(mask_sh)\ argument
153 DPCS_MASK_SH_LIST(mask_sh),\
174 #define LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)\ argument
175 LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh),\
176 LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\
179 LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE0EN, mask_sh),\
183 LE_SF(DIG0_DIG_LANE_ENABLE, DIG_CLK_EN, mask_sh),\
184 LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn32/
A Ddcn32_dio_stream_encoder.h98 #define SE_COMMON_MASK_SH_LIST_DCN32(mask_sh)\ argument
114 SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
135 SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
136 SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
142 SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
144 SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
146 SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
147 SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
168 SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
181 SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\
[all …]
A Ddcn32_optc.h118 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
124 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
131 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
135 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
167 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
190 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
191 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
192 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
204 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
206 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
[all …]
A Ddcn32_mmhubbub.h85 #define MCIF_WB_COMMON_MASK_SH_LIST_DCN32(mask_sh) \ argument
99 SF(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
105 SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
112 SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
119 SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
126 SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
133 SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
140 SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
147 SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\
154 SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ, mask_sh),\
[all …]
A Ddcn32_dccg.h70 #define DCCG_MASK_SH_LIST_DCN32(mask_sh) \ argument
93 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN, mask_sh),\
94 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, mask_sh),\
95 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, mask_sh),\
96 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, mask_sh),\
141 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_SRC_SEL, mask_sh),\
142 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_EN, mask_sh),\
143 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_SRC_SEL, mask_sh),\
144 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_EN, mask_sh),\
146 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\
[all …]
A Ddcn32_hubbub.h93 #define HUBBUB_MASK_SH_LIST_DCN32(mask_sh)\ argument
109 HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
112 HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \
113 HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
114 HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
115 HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
116 HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \
130 HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE, mask_sh),\
132 HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE, mask_sh),\
134 HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE, mask_sh),\
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn314/
A Ddcn314_dccg.h79 #define DCCG_MASK_SH_LIST_DCN314_COMMON(mask_sh) \ argument
88 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN, mask_sh),\
89 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, mask_sh),\
90 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, mask_sh),\
91 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, mask_sh),\
136 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_EN, mask_sh),\
138 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_EN, mask_sh),\
140 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\
142 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\
161 #define DCCG_MASK_SH_LIST_DCN314(mask_sh) \ argument
[all …]
A Ddcn314_optc.h119 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
125 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
132 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
136 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
168 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
191 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
192 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
193 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
205 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
207 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
[all …]
A Ddcn314_dio_stream_encoder.h113 #define SE_COMMON_MASK_SH_LIST_DCN314(mask_sh)\ argument
129 SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
150 SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
151 SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
157 SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
159 SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
161 SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
162 SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
183 SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
196 SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_aux.h93 #define DCE10_AUX_MASK_SH_LIST(mask_sh)\ argument
94 AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\
100 AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
104 AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
115 #define DCE_AUX_MASK_SH_LIST(mask_sh)\ argument
116 AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\
117 AUX_SF(AUX_CONTROL, AUX_RESET, mask_sh),\
128 AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
139 #define DCE12_AUX_MASK_SH_LIST(mask_sh)\ argument
165 #define DCN10_AUX_MASK_SH_LIST(mask_sh)\ argument
[all …]
A Ddce_opp.h121 OPP_SF(FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\
130 OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\
134 #define OPP_COMMON_MASK_SH_LIST_DCE_110(mask_sh)\ argument
135 OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
140 #define OPP_COMMON_MASK_SH_LIST_DCE_100(mask_sh)\ argument
146 #define OPP_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ argument
157 #define OPP_COMMON_MASK_SH_LIST_DCE_80(mask_sh)\ argument
158 OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)
160 #define OPP_COMMON_MASK_SH_LIST_DCE_120(mask_sh)\ argument
206 #define OPP_COMMON_MASK_SH_LIST_DCE_60(mask_sh)\ argument
[all …]
A Ddce_ipp.h69 IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \
70 IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \
77 IPP_SF(CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \
79 IPP_SF(CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \
82 IPP_SF(CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \
83 IPP_SF(CUR_SIZE, CURSOR_WIDTH, mask_sh), \
84 IPP_SF(CUR_SIZE, CURSOR_HEIGHT, mask_sh), \
153 IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \
154 IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \
167 IPP_SF(CUR_SIZE, CURSOR_WIDTH, mask_sh), \
[all …]
A Ddce_transform.h190 XFM_SF(DENORM_CONTROL, DENORM_MODE, mask_sh), \
191 XFM_SF(LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \
221 XFM_SF(SCL_MODE, SCL_MODE, mask_sh), \
252 XFM_SF(LB_DATA_FORMAT, ALPHA_EN, mask_sh)
254 #define XFM_COMMON_MASK_SH_LIST_DCE80(mask_sh) \ argument
267 XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh)
270 #define XFM_COMMON_MASK_SH_LIST_DCE60(mask_sh) \ argument
284 XFM_SF(DENORM_CONTROL, DENORM_MODE, mask_sh), \
285 XFM_SF(DATA_FORMAT, INTERLEAVE_EN, mask_sh), \
391 XFM_SF(SCL0_SCL_MODE, SCL_MODE, mask_sh), \
[all …]
A Ddce_stream_encoder.h147 SE_SF(HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
167 SE_SF(DP_VID_N, DP_VID_N, mask_sh),\
168 SE_SF(DP_VID_M, DP_VID_M, mask_sh),\
169 SE_SF(DIG_FE_CNTL, DIG_START, mask_sh),\
197 SE_SF(DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
206 #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ argument
247 SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
248 SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
291 SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
315 SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_hubbub.h55 #define HUBBUB_MASK_SH_LIST_HVM(mask_sh) \ argument
82 HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh), \
101 #define HUBBUB_MASK_SH_LIST_DCN21(mask_sh)\ argument
102 HUBBUB_MASK_SH_LIST_HVM(mask_sh), \
103 HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
104 HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
107 HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \
108 HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
109 HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
110 HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
[all …]
A Ddcn21_hubp.h44 #define HUBP_MASK_SH_LIST_DCN21_COMMON(mask_sh)\ argument
45 HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\
46 HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
58 HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
59 HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
71 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \
74 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \
81 HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\
91 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
100 #define HUBP_MASK_SH_LIST_DCN21(mask_sh)\ argument
[all …]

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