Searched refs:max_lane_count (Results 1 – 10 of 10) sorted by relevance
54 u32 max_lane_count; member180 err = ps8622_set(cl, 0x01, 0x02, 0x80 | ps8622->max_lane_count); in ps8622_send_config()488 ps8622->max_lane_count = id->driver_data; in ps8622_probe()492 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()493 } else if (ps8622->lane_count > ps8622->max_lane_count) { in ps8622_probe()496 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
440 u32 max_lane_count; member1469 it6505->max_lane_count); in it6505_parse_link_capabilities()3125 u32 *max_lane_count = &it6505->max_lane_count; in it6505_parse_dt() local3152 *max_lane_count = len; in it6505_parse_dt()3154 *max_lane_count = MAX_LANE_COUNT; in it6505_parse_dt()3158 *max_lane_count = MAX_LANE_COUNT; in it6505_parse_dt()3189 it6505->afe_setting, it6505->max_lane_count); in it6505_parse_dt()
324 int max_lane_count = 4; in cdv_intel_dp_max_lane_count() local327 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; in cdv_intel_dp_max_lane_count()328 switch (max_lane_count) { in cdv_intel_dp_max_lane_count()332 max_lane_count = 4; in cdv_intel_dp_max_lane_count()335 return max_lane_count; in cdv_intel_dp_max_lane_count()899 int max_lane_count = cdv_intel_dp_max_lane_count(intel_encoder); in cdv_intel_dp_mode_fixup() local911 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup()929 intel_dp->lane_count = max_lane_count; in cdv_intel_dp_mode_fixup()
28 int min_lane_count, max_lane_count; member
73 crtc_state->lane_count = limits->max_lane_count; in intel_dp_mst_find_vcpi_slots_for_bpp()304 limits.max_lane_count = intel_dp_max_lane_count(intel_dp); in intel_dp_mst_compute_config()
1310 limits->min_lane_count = limits->max_lane_count = in intel_dp_adjust_compliance_config()1363 lane_count <= limits->max_lane_count; in intel_dp_compute_link_config_wide()1527 pipe_config->lane_count = limits->max_lane_count; in intel_dp_dsc_compute_config()1638 limits.max_lane_count = intel_dp_max_lane_count(intel_dp); in intel_dp_compute_link_config()1652 limits.min_lane_count = limits.max_lane_count; in intel_dp_compute_link_config()1660 limits.max_lane_count, limits.max_rate, in intel_dp_compute_link_config()
207 union max_lane_count { union1157 uint8_t max_lane_count; member1197 union max_lane_count max_ln_count;
143 enum link_lane_count_type max_lane_count; member
793 return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count, in analogix_dp_train_link()1647 video_info->max_lane_count = 0x04; in analogix_dp_dt_parse_pdata()1657 &video_info->max_lane_count); in analogix_dp_dt_parse_pdata()
360 link->dpcd_caps.lttpr_caps.max_lane_count > 0 && in dp_is_lttpr_present()361 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 && in dp_is_lttpr_present()1484 link->dpcd_caps.lttpr_caps.max_lane_count = in dp_retrieve_lttpr_cap()2060 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count) in dp_get_max_link_cap()2061 max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count; in dp_get_max_link_cap()
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