Searched refs:max_ref_div (Results 1 – 7 of 7) sorted by relevance
305 dcpll->max_ref_div = 0x3ff; in radeon_get_clock_info()311 p1pll->max_ref_div = 0x3ff; in radeon_get_clock_info()317 p2pll->max_ref_div = 0x3ff; in radeon_get_clock_info()326 spll->max_ref_div = 0xff; in radeon_get_clock_info()335 mpll->max_ref_div = 0xff; in radeon_get_clock_info()
995 ref_div_max = min(pll->max_ref_div, 7u); in radeon_compute_pll_avivo()997 ref_div_max = pll->max_ref_div; in radeon_compute_pll_avivo()1118 uint32_t max_ref_div = pll->max_ref_div; in radeon_compute_pll_legacy() local1134 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); in radeon_compute_pll_legacy()1149 min_ref_div = max_ref_div = pll->reference_div; in radeon_compute_pll_legacy()1151 while (min_ref_div < max_ref_div-1) { in radeon_compute_pll_legacy()1152 uint32_t mid = (min_ref_div + max_ref_div) / 2; in radeon_compute_pll_legacy()1155 max_ref_div = mid; in radeon_compute_pll_legacy()1190 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { in radeon_compute_pll_legacy()
183 uint32_t max_ref_div; member
159 ref_div_max = pll->max_ref_div; in amdgpu_pll_compute()
681 spll->max_ref_div = 0xff; in amdgpu_atomfirmware_get_clock_info()704 mpll->max_ref_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
208 uint32_t max_ref_div; member
607 ppll->max_ref_div = 0x3ff; in amdgpu_atombios_get_clock_info()637 spll->max_ref_div = 0xff; in amdgpu_atombios_get_clock_info()669 mpll->max_ref_div = 0xff; in amdgpu_atombios_get_clock_info()
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