| /linux-6.3-rc2/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| A D | smu7_hwmgr.c | 823 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = in smu7_setup_dpm_tables_v0()
919 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = in smu7_setup_dpm_tables_v1()
921 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = in smu7_setup_dpm_tables_v1()
1514 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; in smu7_populate_umdpstate_clocks()
1555 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; in smu7_populate_umdpstate_clocks()
4080 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); in smu7_find_dpm_states_clocks_in_dpm_table() local
4956 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); in smu7_print_clock_levels() local
5119 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); in smu7_get_mclk_od() local
5122 int value = mclk_table->dpm_levels[mclk_table->count - 1].value; in smu7_get_mclk_od()
5405 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); in smu7_get_max_high_clocks() local
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| A D | vega10_processpptables.c | 601 phm_ppt_v1_clock_voltage_dependency_table *mclk_table; in get_mclk_voltage_dependency_table() local
606 mclk_table = kzalloc(struct_size(mclk_table, entries, mclk_dep_table->ucNumEntries), in get_mclk_voltage_dependency_table()
608 if (!mclk_table) in get_mclk_voltage_dependency_table()
611 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; in get_mclk_voltage_dependency_table()
614 mclk_table->entries[i].vddInd = in get_mclk_voltage_dependency_table()
616 mclk_table->entries[i].vddciInd = in get_mclk_voltage_dependency_table()
618 mclk_table->entries[i].mvddInd = in get_mclk_voltage_dependency_table()
620 mclk_table->entries[i].clk = in get_mclk_voltage_dependency_table()
624 *pp_vega10_mclk_dep_table = mclk_table; in get_mclk_voltage_dependency_table()
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| A D | smu10_hwmgr.c | 976 struct smu10_voltage_dependency_table *mclk_table = in smu10_force_clock_level() local
1006 if (low > mclk_table->count - 1 || high > mclk_table->count - 1) in smu10_force_clock_level()
1011 mclk_table->entries[low].clk/100, in smu10_force_clock_level()
1016 mclk_table->entries[high].clk/100, in smu10_force_clock_level()
1031 struct smu10_voltage_dependency_table *mclk_table = in smu10_print_clock_levels() local
1062 for (i = 0; i < mclk_table->count; i++) in smu10_print_clock_levels()
1065 mclk_table->entries[i].clk / 100, in smu10_print_clock_levels()
1066 ((mclk_table->entries[i].clk / 100) in smu10_print_clock_levels()
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| A D | vega10_hwmgr.c | 696 mclk_table->entries[entry_id].vddc = in vega10_patch_voltage_dependency_tables_with_lookup_table()
699 mclk_table->entries[entry_id].vddci = in vega10_patch_voltage_dependency_tables_with_lookup_table()
702 mclk_table->entries[entry_id].mvdd = in vega10_patch_voltage_dependency_tables_with_lookup_table()
3440 for (i = 0; i < mclk_table->count; i++) { in vega10_find_dpm_states_clocks_in_dpm_table()
3445 if (i >= mclk_table->count) { in vega10_find_dpm_states_clocks_in_dpm_table()
3448 mclk_table->dpm_levels[i-1].value = mclk; in vega10_find_dpm_states_clocks_in_dpm_table()
4049 if (mclk_table == NULL || mclk_table->count == 0) in vega10_get_uclk_index()
4052 count = (uint8_t)(mclk_table->count); in vega10_get_uclk_index()
4690 for (i = 0; i < mclk_table->count; i++) in vega10_emit_clock_levels()
4831 for (i = 0; i < mclk_table->count; i++) in vega10_print_clock_levels()
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| A D | process_pptables_v1_0.c | 367 phm_ppt_v1_clock_voltage_dependency_table *mclk_table; in get_mclk_voltage_dependency_table() local
374 mclk_table = kzalloc(struct_size(mclk_table, entries, mclk_dep_table->ucNumEntries), in get_mclk_voltage_dependency_table()
376 if (!mclk_table) in get_mclk_voltage_dependency_table()
379 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; in get_mclk_voltage_dependency_table()
384 entries, mclk_table, i); in get_mclk_voltage_dependency_table()
395 *pp_tonga_mclk_dep_table = mclk_table; in get_mclk_voltage_dependency_table()
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| A D | smu7_hwmgr.h | 105 struct smu7_single_dpm_table mclk_table; member
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| A D | vega12_hwmgr.c | 2712 struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
2715 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
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| A D | vega20_hwmgr.c | 1515 struct vega20_single_dpm_table *mclk_table = in vega20_get_mclk_od() local
1519 int value = mclk_table->dpm_levels[mclk_table->count - 1].value; in vega20_get_mclk_od()
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| /linux-6.3-rc2/drivers/gpu/drm/radeon/ |
| A D | ci_dpm.c | 3428 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
3453 pi->dpm_table.mclk_table.count = 0; in ci_setup_default_dpm_tables()
3456 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != in ci_setup_default_dpm_tables()
3458 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = in ci_setup_default_dpm_tables()
3460 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = in ci_setup_default_dpm_tables()
3462 pi->dpm_table.mclk_table.count++; in ci_setup_default_dpm_tables()
3731 &pi->dpm_table.mclk_table, in ci_trim_dpm_states()
3823 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; in ci_find_dpm_states_clocks_in_dpm_table() local
3850 if (i >= mclk_table->count) in ci_find_dpm_states_clocks_in_dpm_table()
3875 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()
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| A D | ci_dpm.h | 70 struct ci_single_dpm_table mclk_table; member
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| /linux-6.3-rc2/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| A D | iceland_smumgr.c | 1361 for (i = 0; i < dpm_table->mclk_table.count; i++) { in iceland_populate_all_memory_levels()
1362 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in iceland_populate_all_memory_levels()
1364 result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in iceland_populate_all_memory_levels()
1382 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; in iceland_populate_all_memory_levels()
1383 …vel_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in iceland_populate_all_memory_levels()
1622 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in iceland_program_memory_timing_parameters()
1625 data->dpm_table.mclk_table.dpm_levels[j].value, in iceland_program_memory_timing_parameters()
1667 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in iceland_populate_smc_boot_level()
1761 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { in iceland_convert_mc_reg_table_to_smc()
1764 data->dpm_table.mclk_table.dpm_levels[i].value, in iceland_convert_mc_reg_table_to_smc()
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| A D | vegam_smumgr.c | 1050 for (i = 0; i < dpm_table->mclk_table.count; i++) { in vegam_populate_all_memory_levels()
1051 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in vegam_populate_all_memory_levels()
1055 dpm_table->mclk_table.dpm_levels[i].value, in vegam_populate_all_memory_levels()
1068 (uint8_t)dpm_table->mclk_table.count; in vegam_populate_all_memory_levels()
1070 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in vegam_populate_all_memory_levels()
1072 for (i = 0; i < dpm_table->mclk_table.count; i++) in vegam_populate_all_memory_levels()
1076 levels[dpm_table->mclk_table.count - 1].DisplayWatermark = in vegam_populate_all_memory_levels()
1289 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { in vegam_program_memory_timing_parameters()
1292 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in vegam_program_memory_timing_parameters()
1381 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in vegam_populate_smc_boot_level()
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| A D | fiji_smumgr.c | 1234 for (i = 0; i < dpm_table->mclk_table.count; i++) { in fiji_populate_all_memory_levels()
1235 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in fiji_populate_all_memory_levels()
1239 dpm_table->mclk_table.dpm_levels[i].value, in fiji_populate_all_memory_levels()
1257 (uint8_t)dpm_table->mclk_table.count; in fiji_populate_all_memory_levels()
1259 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in fiji_populate_all_memory_levels()
1261 levels[dpm_table->mclk_table.count - 1].DisplayWatermark = in fiji_populate_all_memory_levels()
1374 data->dpm_table.mclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1395 data->dpm_table.mclk_table.dpm_levels[0].value, in fiji_populate_smc_acpi_level()
1533 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in fiji_program_memory_timing_parameters()
1536 data->dpm_table.mclk_table.dpm_levels[j].value, in fiji_program_memory_timing_parameters()
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| A D | ci_smumgr.c | 1316 for (i = 0; i < dpm_table->mclk_table.count; i++) { in ci_populate_all_memory_levels()
1317 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in ci_populate_all_memory_levels()
1319 result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
1329 if ((dpm_table->mclk_table.count >= 2) in ci_populate_all_memory_levels()
1339 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
1661 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in ci_program_memory_timing_parameters()
1664 data->dpm_table.mclk_table.dpm_levels[j].value, in ci_program_memory_timing_parameters()
1706 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in ci_populate_smc_boot_level()
1796 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { in ci_convert_mc_reg_table_to_smc()
1799 data->dpm_table.mclk_table.dpm_levels[i].value, in ci_convert_mc_reg_table_to_smc()
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| A D | polaris10_smumgr.c | 1223 for (i = 0; i < dpm_table->mclk_table.count; i++) { in polaris10_populate_all_memory_levels()
1224 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in polaris10_populate_all_memory_levels()
1228 dpm_table->mclk_table.dpm_levels[i].value, in polaris10_populate_all_memory_levels()
1230 if (i == dpm_table->mclk_table.count - 1) in polaris10_populate_all_memory_levels()
1237 (uint8_t)dpm_table->mclk_table.count; in polaris10_populate_all_memory_levels()
1239 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in polaris10_populate_all_memory_levels()
1340 data->dpm_table.mclk_table.dpm_levels[0].value, in polaris10_populate_smc_acpi_level()
1499 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { in polaris10_program_memory_timing_parameters()
1502 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in polaris10_program_memory_timing_parameters()
1505 result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j); in polaris10_program_memory_timing_parameters()
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| A D | tonga_smumgr.c | 1107 for (i = 0; i < dpm_table->mclk_table.count; i++) { in tonga_populate_all_memory_levels()
1108 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in tonga_populate_all_memory_levels()
1113 dpm_table->mclk_table.dpm_levels[i].value, in tonga_populate_all_memory_levels()
1130 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; in tonga_populate_all_memory_levels()
1131 …vel_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in tonga_populate_all_memory_levels()
1498 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in tonga_program_memory_timing_parameters()
1501 data->dpm_table.mclk_table.dpm_levels[j].value, in tonga_program_memory_timing_parameters()
1545 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in tonga_populate_smc_boot_level()
2140 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { in tonga_convert_mc_reg_table_to_smc()
2143 data->dpm_table.mclk_table.dpm_levels[i].value, in tonga_convert_mc_reg_table_to_smc()
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