Searched refs:memoryClock (Results 1 – 13 of 13) sorted by relevance
212 hwmgr->platform_descriptor.overdriveLimit.memoryClock = in init_powerplay_table_information()229 && hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0) in init_powerplay_table_information()
348 hwmgr->platform_descriptor.overdriveLimit.memoryClock : in vega10_odn_initial_default_setting()912 hwmgr->platform_descriptor.clockStep.memoryClock = 500; in vega10_hwmgr_backend_init()1366 hwmgr->platform_descriptor.overdriveLimit.memoryClock = in vega10_setup_default_dpm_tables()1819 hwmgr->platform_descriptor.overdriveLimit.memoryClock; in vega10_populate_single_memory_level()3341 minimum_clocks.memoryClock = stable_pstate_mclk; in vega10_apply_state_adjust_rules()3366 if (mclk < minimum_clocks.memoryClock) in vega10_apply_state_adjust_rules()3367 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? in vega10_apply_state_adjust_rules()3368 max_limits->mclk : minimum_clocks.memoryClock; in vega10_apply_state_adjust_rules()4107 if (min_clocks.memoryClock != 0) { in vega10_notify_smc_display_config_after_ps_adjustment()5196 hwmgr->platform_descriptor.overdriveLimit.memoryClock) { in vega10_set_mclk_od()[all …]
927 if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) in smu7_setup_dpm_tables_v1()928 hwmgr->platform_descriptor.overdriveLimit.memoryClock = dep_mclk_table->entries[i-1].clk; in smu7_setup_dpm_tables_v1()3026 hwmgr->platform_descriptor.clockStep.memoryClock = 500; in smu7_hwmgr_backend_init()3364 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in smu7_apply_state_adjust_rules()3387 minimum_clocks.memoryClock = stable_pstate_mclk; in smu7_apply_state_adjust_rules()3422 if (mclk < minimum_clocks.memoryClock) in smu7_apply_state_adjust_rules()3423 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? in smu7_apply_state_adjust_rules()3424 max_limits->mclk : minimum_clocks.memoryClock; in smu7_apply_state_adjust_rules()5037 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); in smu7_print_clock_levels()5462 hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) { in smu7_check_clk_voltage_valid()[all …]
1120 hwmgr->platform_descriptor.overdriveLimit.memoryClock = in init_overdrive_limits_V1_4()1156 hwmgr->platform_descriptor.overdriveLimit.memoryClock = le32_to_cpu(header->ulMaxMemoryClock); in init_overdrive_limits_V2_1()1176 hwmgr->platform_descriptor.overdriveLimit.memoryClock = 0; in init_overdrive_limits()
1082 clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ? in smu8_apply_state_adjust_rules()1088 clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk; in smu8_apply_state_adjust_rules()1090 force_high = (clocks.memoryClock > data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1]) in smu8_apply_state_adjust_rules()
586 hwmgr->platform_descriptor.clockStep.memoryClock = 500; in smu10_hwmgr_backend_init()
470 hwmgr->platform_descriptor.clockStep.memoryClock = 500; in vega20_hwmgr_backend_init()2341 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega20_notify_smc_display_config_after_ps_adjustment()2360 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100; in vega20_notify_smc_display_config_after_ps_adjustment()
428 hwmgr->platform_descriptor.clockStep.memoryClock = 500; in vega12_hwmgr_backend_init()1622 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega12_notify_smc_display_config_after_ps_adjustment()
891 hwmgr->platform_descriptor.overdriveLimit.memoryClock = in init_over_drive_limits()
331 hwmgr->platform_descriptor.overdriveLimit.memoryClock = in init_over_drive_limits()
328 uint32_t memoryClock; member
757 unsigned int memoryClock; member
4475 info->memoryClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz; in get_clock_requirements_for_state()
Completed in 83 milliseconds