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Searched refs:mipi_dsi_dcs_write_seq (Results 1 – 16 of 16) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/panel/
A Dpanel-newvision-nv3051d.c55 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x30); in panel_nv3051d_init_sequence()
56 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x52); in panel_nv3051d_init_sequence()
57 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x01); in panel_nv3051d_init_sequence()
58 mipi_dsi_dcs_write_seq(dsi, 0xE3, 0x00); in panel_nv3051d_init_sequence()
59 mipi_dsi_dcs_write_seq(dsi, 0x03, 0x40); in panel_nv3051d_init_sequence()
60 mipi_dsi_dcs_write_seq(dsi, 0x04, 0x00); in panel_nv3051d_init_sequence()
61 mipi_dsi_dcs_write_seq(dsi, 0x05, 0x03); in panel_nv3051d_init_sequence()
62 mipi_dsi_dcs_write_seq(dsi, 0x24, 0x12); in panel_nv3051d_init_sequence()
63 mipi_dsi_dcs_write_seq(dsi, 0x25, 0x1E); in panel_nv3051d_init_sequence()
64 mipi_dsi_dcs_write_seq(dsi, 0x26, 0x28); in panel_nv3051d_init_sequence()
[all …]
A Dpanel-visionox-vtdr6130.c55 mipi_dsi_dcs_write_seq(dsi, 0x59, 0x09); in visionox_vtdr6130_on()
56 mipi_dsi_dcs_write_seq(dsi, 0x6c, 0x01); in visionox_vtdr6130_on()
57 mipi_dsi_dcs_write_seq(dsi, 0x6d, 0x00); in visionox_vtdr6130_on()
58 mipi_dsi_dcs_write_seq(dsi, 0x6f, 0x01); in visionox_vtdr6130_on()
59 mipi_dsi_dcs_write_seq(dsi, 0x70, in visionox_vtdr6130_on()
72 mipi_dsi_dcs_write_seq(dsi, 0xb1, in visionox_vtdr6130_on()
77 mipi_dsi_dcs_write_seq(dsi, 0xce, in visionox_vtdr6130_on()
83 mipi_dsi_dcs_write_seq(dsi, 0xb4, in visionox_vtdr6130_on()
86 mipi_dsi_dcs_write_seq(dsi, 0xb5, in visionox_vtdr6130_on()
89 mipi_dsi_dcs_write_seq(dsi, 0xbc, in visionox_vtdr6130_on()
[all …]
A Dpanel-leadtek-ltk050h3146w.c256 mipi_dsi_dcs_write_seq(dsi, 0xdf, 0x93, 0x65, 0xf8); in ltk050h3146w_init_sequence()
259 mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x00, 0xb5); in ltk050h3146w_init_sequence()
260 mipi_dsi_dcs_write_seq(dsi, 0xb3, 0x00, 0xb5); in ltk050h3146w_init_sequence()
266 mipi_dsi_dcs_write_seq(dsi, 0xbc, 0x0f, 0x04); in ltk050h3146w_init_sequence()
267 mipi_dsi_dcs_write_seq(dsi, 0xbe, 0x1e, 0xf2); in ltk050h3146w_init_sequence()
268 mipi_dsi_dcs_write_seq(dsi, 0xc0, 0x26, 0x03); in ltk050h3146w_init_sequence()
269 mipi_dsi_dcs_write_seq(dsi, 0xc1, 0x00, 0x12); in ltk050h3146w_init_sequence()
298 mipi_dsi_dcs_write_seq(dsi, 0xde, 0x02); in ltk050h3146w_init_sequence()
299 mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x32, 0x1c); in ltk050h3146w_init_sequence()
301 mipi_dsi_dcs_write_seq(dsi, 0xc1, 0x11); in ltk050h3146w_init_sequence()
[all …]
A Dpanel-xinpeng-xpp055c272.c73 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETMIPI, in xpp055c272_init_sequence()
80 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETRGBIF, in xpp055c272_init_sequence()
83 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETSCR, in xpp055c272_init_sequence()
86 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETVDC, 0x46); in xpp055c272_init_sequence()
87 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPANEL, 0x0b); in xpp055c272_init_sequence()
88 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETCYC, 0x80); in xpp055c272_init_sequence()
90 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETEQ, in xpp055c272_init_sequence()
93 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPOWER, in xpp055c272_init_sequence()
102 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETGIP1, in xpp055c272_init_sequence()
111 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETGIP2, in xpp055c272_init_sequence()
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A Dpanel-himax-hx8394.c94 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETEXTC, in hsd060bhw4_init_sequence()
98 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER, in hsd060bhw4_init_sequence()
102 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETMIPI, in hsd060bhw4_init_sequence()
106 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETDISP, in hsd060bhw4_init_sequence()
110 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCYC, in hsd060bhw4_init_sequence()
116 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP0, in hsd060bhw4_init_sequence()
123 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP1, in hsd060bhw4_init_sequence()
131 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP2, in hsd060bhw4_init_sequence()
139 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGAMMA, in hsd060bhw4_init_sequence()
149 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPANEL, in hsd060bhw4_init_sequence()
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A Dpanel-sitronix-st7703.c168 mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI, in xbd599_init_sequence()
187 mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF, in xbd599_init_sequence()
198 mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR, in xbd599_init_sequence()
222 mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP, in xbd599_init_sequence()
232 mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETEQ, in xbd599_init_sequence()
255 mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER, in xbd599_init_sequence()
273 mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETBGP, in xbd599_init_sequence()
278 mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETVCOM, in xbd599_init_sequence()
286 mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP1, in xbd599_init_sequence()
297 mipi_dsi_dcs_write_seq(dsi, ST7703_CMD_SETGIP2, in xbd599_init_sequence()
[all …]
A Dpanel-elida-kd35t133.c63 mipi_dsi_dcs_write_seq(dsi, KD35T133_CMD_POSITIVEGAMMA, in kd35t133_init_sequence()
66 mipi_dsi_dcs_write_seq(dsi, KD35T133_CMD_NEGATIVEGAMMA, in kd35t133_init_sequence()
69 mipi_dsi_dcs_write_seq(dsi, KD35T133_CMD_POWERCONTROL1, 0x18, 0x17); in kd35t133_init_sequence()
70 mipi_dsi_dcs_write_seq(dsi, KD35T133_CMD_POWERCONTROL2, 0x41); in kd35t133_init_sequence()
72 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE, 0x48); in kd35t133_init_sequence()
73 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PIXEL_FORMAT, 0x55); in kd35t133_init_sequence()
74 mipi_dsi_dcs_write_seq(dsi, KD35T133_CMD_INTERFACEMODECTRL, 0x00); in kd35t133_init_sequence()
75 mipi_dsi_dcs_write_seq(dsi, KD35T133_CMD_FRAMERATECTRL, 0xa0); in kd35t133_init_sequence()
77 mipi_dsi_dcs_write_seq(dsi, KD35T133_CMD_DISPLAYFUNCTIONCTRL, in kd35t133_init_sequence()
79 mipi_dsi_dcs_write_seq(dsi, KD35T133_CMD_SETIMAGEFUNCTION, 0x00); in kd35t133_init_sequence()
[all …]
A Dpanel-samsung-s6e88a0-ams452ef01.c49 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); // enable LEVEL2 commands in s6e88a0_ams452ef01_on()
50 mipi_dsi_dcs_write_seq(dsi, 0xcc, 0x4c); // set Pixel Clock Divider polarity in s6e88a0_ams452ef01_on()
60 mipi_dsi_dcs_write_seq(dsi, 0xca, in s6e88a0_ams452ef01_on()
72 mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x40, 0x0a, 0x17, 0x00, 0x0a); in s6e88a0_ams452ef01_on()
73 mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x2c, 0x0b); // set default elvss voltage in s6e88a0_ams452ef01_on()
74 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); in s6e88a0_ams452ef01_on()
75 mipi_dsi_dcs_write_seq(dsi, 0xf7, 0x03); // gamma/aor update in s6e88a0_ams452ef01_on()
76 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); // disable LEVEL2 commands in s6e88a0_ams452ef01_on()
A Dpanel-boe-bf060y8m-aj0.c62 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0xa5, 0x00); in boe_bf060y8m_aj0_on()
63 mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x00, 0x4c); in boe_bf060y8m_aj0_on()
64 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_3D_CONTROL, 0x10); in boe_bf060y8m_aj0_on()
65 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, DCS_ALLOW_HBM_RANGE); in boe_bf060y8m_aj0_on()
66 mipi_dsi_dcs_write_seq(dsi, 0xf8, in boe_bf060y8m_aj0_on()
76 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0xa5, 0x00); in boe_bf060y8m_aj0_on()
77 mipi_dsi_dcs_write_seq(dsi, 0xc0, in boe_bf060y8m_aj0_on()
80 mipi_dsi_dcs_write_seq(dsi, 0xc1, 0x00, 0x00, 0x00, 0x1f, 0x1f, in boe_bf060y8m_aj0_on()
83 mipi_dsi_dcs_write_seq(dsi, 0xe2, 0x20, 0x04, 0x10, 0x12, 0x92, in boe_bf060y8m_aj0_on()
86 mipi_dsi_dcs_write_seq(dsi, 0xde, 0x01, 0x2c, 0x00, 0x77, 0x3e); in boe_bf060y8m_aj0_on()
A Dpanel-samsung-sofef00.c61 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); in sofef00_panel_on()
69 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); in sofef00_panel_on()
70 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); in sofef00_panel_on()
71 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x07); in sofef00_panel_on()
72 mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x12); in sofef00_panel_on()
73 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); in sofef00_panel_on()
74 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x20); in sofef00_panel_on()
75 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); in sofef00_panel_on()
A Dpanel-jdi-fhd-r63452.c63 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE, 0x00); in jdi_fhd_r63452_on()
95 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x24); in jdi_fhd_r63452_on()
96 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); in jdi_fhd_r63452_on()
97 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, 0x00); in jdi_fhd_r63452_on()
98 mipi_dsi_dcs_write_seq(dsi, 0x84, 0x00); in jdi_fhd_r63452_on()
115 mipi_dsi_dcs_write_seq(dsi, 0x84, 0x00); in jdi_fhd_r63452_on()
A Dpanel-ebbg-ft8719.c71 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x24); in ebbg_ft8719_on()
72 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); in ebbg_ft8719_on()
A Dpanel-sharp-ls060t1sx01.c53 mipi_dsi_dcs_write_seq(dsi, 0xbb, 0x13); in sharp_ls060_on()
54 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_MEMORY_START); in sharp_ls060_on()
A Dpanel-novatek-nt35950.c333 mipi_dsi_dcs_write_seq(dsi, 0xd4, 0x88, 0x88); in nt35950_on()
341 mipi_dsi_dcs_write_seq(dsi, MCS_PARAM_SPR_EN, 0x01); in nt35950_on()
344 mipi_dsi_dcs_write_seq(dsi, MCS_PARAM_SPR_MODE, MCS_SPR_MODE_YYG_RAINBOW_RGB); in nt35950_on()
A Dpanel-asus-z00t-tm5p5-n35596.c104 mipi_dsi_dcs_write_seq(dsi, 0x4f, 0x01); in tm5p5_nt35596_off()
/linux-6.3-rc2/include/drm/
A Ddrm_mipi_dsi.h325 #define mipi_dsi_dcs_write_seq(dsi, cmd, seq...) \ macro

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