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Searched refs:misc_base (Results 1 – 5 of 5) sorted by relevance

/linux-6.3-rc2/include/linux/clk/
A Dspear.h12 void __init spear3xx_clk_init(void __iomem *misc_base,
15 static inline void __init spear3xx_clk_init(void __iomem *misc_base, in spear3xx_clk_init() argument
20 void __init spear6xx_clk_init(void __iomem *misc_base);
22 static inline void __init spear6xx_clk_init(void __iomem *misc_base) {} in spear6xx_clk_init() argument
26 void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base);
28 static inline void spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) {} in spear1310_clk_init() argument
32 void __init spear1340_clk_init(void __iomem *misc_base);
34 static inline void spear1340_clk_init(void __iomem *misc_base) {} in spear1340_clk_init() argument
/linux-6.3-rc2/drivers/clk/spear/
A Dspear6xx_clock.c17 #define PLL1_CTR (misc_base + 0x008)
18 #define PLL1_FRQ (misc_base + 0x00C)
19 #define PLL2_CTR (misc_base + 0x014)
20 #define PLL2_FRQ (misc_base + 0x018)
21 #define PLL_CLK_CFG (misc_base + 0x020)
26 #define CORE_CLK_CFG (misc_base + 0x024)
33 #define PERIP_CLK_CFG (misc_base + 0x028)
47 #define PERIP1_CLK_ENB (misc_base + 0x02C)
73 #define PRSC0_CLK_CFG (misc_base + 0x044)
74 #define PRSC1_CLK_CFG (misc_base + 0x048)
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A Dspear1340_clock.c20 #define SPEAR1340_SYS_CLK_CTRL (misc_base + 0x200)
27 #define SPEAR1340_PLL_CFG (misc_base + 0x210)
39 #define SPEAR1340_PLL1_CTR (misc_base + 0x214)
40 #define SPEAR1340_PLL1_FRQ (misc_base + 0x218)
41 #define SPEAR1340_PLL2_CTR (misc_base + 0x220)
42 #define SPEAR1340_PLL2_FRQ (misc_base + 0x224)
43 #define SPEAR1340_PLL3_CTR (misc_base + 0x22C)
44 #define SPEAR1340_PLL3_FRQ (misc_base + 0x230)
45 #define SPEAR1340_PLL4_CTR (misc_base + 0x238)
46 #define SPEAR1340_PLL4_FRQ (misc_base + 0x23C)
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A Dspear3xx_clock.c20 #define PLL1_CTR (misc_base + 0x008)
21 #define PLL1_FRQ (misc_base + 0x00C)
22 #define PLL2_CTR (misc_base + 0x014)
23 #define PLL2_FRQ (misc_base + 0x018)
24 #define PLL_CLK_CFG (misc_base + 0x020)
29 #define CORE_CLK_CFG (misc_base + 0x024)
39 #define PERIP_CLK_CFG (misc_base + 0x028)
50 #define PERIP1_CLK_ENB (misc_base + 0x02C)
69 #define RAS_CLK_ENB (misc_base + 0x034)
82 #define PRSC0_CLK_CFG (misc_base + 0x044)
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A Dspear1310_clock.c20 #define SPEAR1310_PLL_CFG (misc_base + 0x210)
33 #define SPEAR1310_PLL1_CTR (misc_base + 0x214)
34 #define SPEAR1310_PLL1_FRQ (misc_base + 0x218)
35 #define SPEAR1310_PLL2_CTR (misc_base + 0x220)
36 #define SPEAR1310_PLL2_FRQ (misc_base + 0x224)
37 #define SPEAR1310_PLL3_CTR (misc_base + 0x22C)
38 #define SPEAR1310_PLL3_FRQ (misc_base + 0x230)
39 #define SPEAR1310_PLL4_CTR (misc_base + 0x238)
40 #define SPEAR1310_PLL4_FRQ (misc_base + 0x23C)
41 #define SPEAR1310_PERIP_CLK_CFG (misc_base + 0x244)
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