1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef __MLX5_EN_H__
33 #define __MLX5_EN_H__
34
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/crash_dump.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/mlx5/fs.h>
47 #include <linux/rhashtable.h>
48 #include <net/udp_tunnel.h>
49 #include <net/switchdev.h>
50 #include <net/xdp.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
53 #include "wq.h"
54 #include "mlx5_core.h"
55 #include "en_stats.h"
56 #include "en/dcbnl.h"
57 #include "en/fs.h"
58 #include "en/qos.h"
59 #include "lib/hv_vhca.h"
60 #include "lib/clock.h"
61 #include "en/rx_res.h"
62 #include "en/selq.h"
63
64 extern const struct net_device_ops mlx5e_netdev_ops;
65 struct page_pool;
66
67 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
68 #define MLX5E_METADATA_ETHER_LEN 8
69
70 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
71
72 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
73 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
74
75 #define MLX5E_MAX_NUM_TC 8
76 #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE
77
78 #define MLX5_RX_HEADROOM NET_SKB_PAD
79 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
80 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
81
82 #define MLX5E_RX_MAX_HEAD (256)
83 #define MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE (9)
84 #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE)
85 #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE (64)
86 #define MLX5E_SHAMPO_WQ_RESRV_SIZE (64 * 1024)
87 #define MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE (4096)
88
89 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
90 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
91 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
92 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
93 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
94 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
95
96 #define MLX5_MPWRQ_MAX_LOG_WQE_SZ 18
97
98 /* Keep in sync with mlx5e_mpwrq_log_wqe_sz.
99 * These are theoretical maximums, which can be further restricted by
100 * capabilities. These values are used for static resource allocations and
101 * sanity checks.
102 * MLX5_SEND_WQE_MAX_SIZE is a bit bigger than the maximum cacheline-aligned WQE
103 * size actually used at runtime, but it's not a problem when calculating static
104 * array sizes.
105 */
106 #define MLX5_UMR_MAX_FLEX_SPACE \
107 (ALIGN_DOWN(MLX5_SEND_WQE_MAX_SIZE - sizeof(struct mlx5e_umr_wqe), \
108 MLX5_UMR_FLEX_ALIGNMENT))
109 #define MLX5_MPWRQ_MAX_PAGES_PER_WQE \
110 rounddown_pow_of_two(MLX5_UMR_MAX_FLEX_SPACE / sizeof(struct mlx5_mtt))
111
112 #define MLX5E_MAX_RQ_NUM_MTTS \
113 (ALIGN_DOWN(U16_MAX, 4) * 2) /* Fits into u16 and aligned by WQEBB. */
114 #define MLX5E_MAX_RQ_NUM_KSMS (U16_MAX - 1) /* So that num_ksms fits into u16. */
115 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
116
117 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
118 #define MLX5E_LOG_MAX_RX_WQE_BULK \
119 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
120
121 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
122 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
123 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
124
125 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
126 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
127 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
128
129 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
130
131 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
132 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
133
134 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
135 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
136 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
137 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
138 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
139 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
140 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
141 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
142
143 #define MLX5E_MIN_NUM_CHANNELS 0x1
144 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE / 2)
145 #define MLX5E_TX_CQ_POLL_BUDGET 128
146 #define MLX5E_TX_XSK_POLL_BUDGET 64
147 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
148
149 #define MLX5E_KLM_UMR_WQE_SZ(sgl_len)\
150 (sizeof(struct mlx5e_umr_wqe) +\
151 (sizeof(struct mlx5_klm) * (sgl_len)))
152
153 #define MLX5E_KLM_UMR_WQEBBS(klm_entries) \
154 (DIV_ROUND_UP(MLX5E_KLM_UMR_WQE_SZ(klm_entries), MLX5_SEND_WQE_BB))
155
156 #define MLX5E_KLM_UMR_DS_CNT(klm_entries)\
157 (DIV_ROUND_UP(MLX5E_KLM_UMR_WQE_SZ(klm_entries), MLX5_SEND_WQE_DS))
158
159 #define MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size)\
160 (((wqe_size) - sizeof(struct mlx5e_umr_wqe)) / sizeof(struct mlx5_klm))
161
162 #define MLX5E_KLM_ENTRIES_PER_WQE(wqe_size)\
163 ALIGN_DOWN(MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size), MLX5_UMR_KLM_NUM_ENTRIES_ALIGNMENT)
164
165 #define MLX5E_MAX_KLM_PER_WQE(mdev) \
166 MLX5E_KLM_ENTRIES_PER_WQE(MLX5_SEND_WQE_BB * mlx5e_get_max_sq_aligned_wqebbs(mdev))
167
168 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
169
170 #define mlx5e_dbg(mlevel, priv, format, ...) \
171 do { \
172 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
173 netdev_warn(priv->netdev, format, \
174 ##__VA_ARGS__); \
175 } while (0)
176
177 #define mlx5e_state_dereference(priv, p) \
178 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock))
179
mlx5e_get_num_lag_ports(struct mlx5_core_dev * mdev)180 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev)
181 {
182 if (mlx5_lag_is_lacp_owner(mdev))
183 return 1;
184
185 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);
186 }
187
mlx5_min_rx_wqes(int wq_type,u32 wq_size)188 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
189 {
190 switch (wq_type) {
191 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
192 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
193 wq_size / 2);
194 default:
195 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
196 wq_size / 2);
197 }
198 }
199
200 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
mlx5e_get_max_num_channels(struct mlx5_core_dev * mdev)201 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
202 {
203 return is_kdump_kernel() ?
204 MLX5E_MIN_NUM_CHANNELS :
205 min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS);
206 }
207
208 /* The maximum WQE size can be retrieved by max_wqe_sz_sq in
209 * bytes units. Driver hardens the limitation to 1KB (16
210 * WQEBBs), unless firmware capability is stricter.
211 */
mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev * mdev)212 static inline u8 mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev *mdev)
213 {
214 BUILD_BUG_ON(MLX5_SEND_WQE_MAX_WQEBBS > U8_MAX);
215
216 return (u8)min_t(u16, MLX5_SEND_WQE_MAX_WQEBBS,
217 MLX5_CAP_GEN(mdev, max_wqe_sz_sq) / MLX5_SEND_WQE_BB);
218 }
219
mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev * mdev)220 static inline u8 mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev *mdev)
221 {
222 /* The return value will be multiplied by MLX5_SEND_WQEBB_NUM_DS.
223 * Since max_sq_wqebbs may be up to MLX5_SEND_WQE_MAX_WQEBBS == 16,
224 * see mlx5e_get_max_sq_wqebbs(), the multiplication (16 * 4 == 64)
225 * overflows the 6-bit DS field of Ctrl Segment. Use a bound lower
226 * than MLX5_SEND_WQE_MAX_WQEBBS to let a full-session WQE be
227 * cache-aligned.
228 */
229 u8 wqebbs = mlx5e_get_max_sq_wqebbs(mdev);
230
231 wqebbs = min_t(u8, wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1);
232 #if L1_CACHE_BYTES >= 128
233 wqebbs = ALIGN_DOWN(wqebbs, 2);
234 #endif
235 return wqebbs;
236 }
237
238 struct mlx5e_tx_wqe {
239 struct mlx5_wqe_ctrl_seg ctrl;
240 struct mlx5_wqe_eth_seg eth;
241 struct mlx5_wqe_data_seg data[];
242 };
243
244 struct mlx5e_rx_wqe_ll {
245 struct mlx5_wqe_srq_next_seg next;
246 struct mlx5_wqe_data_seg data[];
247 };
248
249 struct mlx5e_rx_wqe_cyc {
250 DECLARE_FLEX_ARRAY(struct mlx5_wqe_data_seg, data);
251 };
252
253 struct mlx5e_umr_wqe {
254 struct mlx5_wqe_ctrl_seg ctrl;
255 struct mlx5_wqe_umr_ctrl_seg uctrl;
256 struct mlx5_mkey_seg mkc;
257 union {
258 DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts);
259 DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms);
260 DECLARE_FLEX_ARRAY(struct mlx5_ksm, inline_ksms);
261 };
262 };
263
264 enum mlx5e_priv_flag {
265 MLX5E_PFLAG_RX_CQE_BASED_MODER,
266 MLX5E_PFLAG_TX_CQE_BASED_MODER,
267 MLX5E_PFLAG_RX_CQE_COMPRESS,
268 MLX5E_PFLAG_RX_STRIDING_RQ,
269 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
270 MLX5E_PFLAG_XDP_TX_MPWQE,
271 MLX5E_PFLAG_SKB_TX_MPWQE,
272 MLX5E_PFLAG_TX_PORT_TS,
273 MLX5E_NUM_PFLAGS, /* Keep last */
274 };
275
276 #define MLX5E_SET_PFLAG(params, pflag, enable) \
277 do { \
278 if (enable) \
279 (params)->pflags |= BIT(pflag); \
280 else \
281 (params)->pflags &= ~(BIT(pflag)); \
282 } while (0)
283
284 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
285
286 enum packet_merge {
287 MLX5E_PACKET_MERGE_NONE,
288 MLX5E_PACKET_MERGE_LRO,
289 MLX5E_PACKET_MERGE_SHAMPO,
290 };
291
292 struct mlx5e_packet_merge_param {
293 enum packet_merge type;
294 u32 timeout;
295 struct {
296 u8 match_criteria_type;
297 u8 alignment_granularity;
298 } shampo;
299 };
300
301 struct mlx5e_params {
302 u8 log_sq_size;
303 u8 rq_wq_type;
304 u8 log_rq_mtu_frames;
305 u16 num_channels;
306 struct {
307 u16 mode;
308 u8 num_tc;
309 struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE];
310 struct {
311 u64 max_rate[TC_MAX_QUEUE];
312 u32 hw_id[TC_MAX_QUEUE];
313 } channel;
314 } mqprio;
315 bool rx_cqe_compress_def;
316 bool tunneled_offload_en;
317 struct dim_cq_moder rx_cq_moderation;
318 struct dim_cq_moder tx_cq_moderation;
319 struct mlx5e_packet_merge_param packet_merge;
320 u8 tx_min_inline_mode;
321 bool vlan_strip_disable;
322 bool scatter_fcs_en;
323 bool rx_dim_enabled;
324 bool tx_dim_enabled;
325 u32 pflags;
326 struct bpf_prog *xdp_prog;
327 struct mlx5e_xsk *xsk;
328 unsigned int sw_mtu;
329 int hard_mtu;
330 bool ptp_rx;
331 };
332
mlx5e_get_dcb_num_tc(struct mlx5e_params * params)333 static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params)
334 {
335 return params->mqprio.mode == TC_MQPRIO_MODE_DCB ?
336 params->mqprio.num_tc : 1;
337 }
338
339 enum {
340 MLX5E_RQ_STATE_ENABLED,
341 MLX5E_RQ_STATE_RECOVERING,
342 MLX5E_RQ_STATE_AM,
343 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
344 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
345 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */
346 MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */
347 MLX5E_RQ_STATE_MINI_CQE_ENHANCED, /* set when enhanced mini_cqe_cap is used */
348 };
349
350 struct mlx5e_cq {
351 /* data path - accessed per cqe */
352 struct mlx5_cqwq wq;
353
354 /* data path - accessed per napi poll */
355 u16 event_ctr;
356 struct napi_struct *napi;
357 struct mlx5_core_cq mcq;
358 struct mlx5e_ch_stats *ch_stats;
359
360 /* control */
361 struct net_device *netdev;
362 struct mlx5_core_dev *mdev;
363 struct mlx5e_priv *priv;
364 struct mlx5_wq_ctrl wq_ctrl;
365 } ____cacheline_aligned_in_smp;
366
367 struct mlx5e_cq_decomp {
368 /* cqe decompression */
369 struct mlx5_cqe64 title;
370 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
371 u8 mini_arr_idx;
372 u16 left;
373 u16 wqe_counter;
374 bool last_cqe_title;
375 } ____cacheline_aligned_in_smp;
376
377 enum mlx5e_dma_map_type {
378 MLX5E_DMA_MAP_SINGLE,
379 MLX5E_DMA_MAP_PAGE
380 };
381
382 struct mlx5e_sq_dma {
383 dma_addr_t addr;
384 u32 size;
385 enum mlx5e_dma_map_type type;
386 };
387
388 enum {
389 MLX5E_SQ_STATE_ENABLED,
390 MLX5E_SQ_STATE_MPWQE,
391 MLX5E_SQ_STATE_RECOVERING,
392 MLX5E_SQ_STATE_IPSEC,
393 MLX5E_SQ_STATE_AM,
394 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE,
395 MLX5E_SQ_STATE_PENDING_XSK_TX,
396 MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC,
397 MLX5E_SQ_STATE_XDP_MULTIBUF,
398 };
399
400 struct mlx5e_tx_mpwqe {
401 /* Current MPWQE session */
402 struct mlx5e_tx_wqe *wqe;
403 u32 bytes_count;
404 u8 ds_count;
405 u8 pkt_count;
406 u8 inline_on;
407 };
408
409 struct mlx5e_skb_fifo {
410 struct sk_buff **fifo;
411 u16 *pc;
412 u16 *cc;
413 u16 mask;
414 };
415
416 struct mlx5e_ptpsq;
417
418 struct mlx5e_txqsq {
419 /* data path */
420
421 /* dirtied @completion */
422 u16 cc;
423 u16 skb_fifo_cc;
424 u32 dma_fifo_cc;
425 struct dim dim; /* Adaptive Moderation */
426
427 /* dirtied @xmit */
428 u16 pc ____cacheline_aligned_in_smp;
429 u16 skb_fifo_pc;
430 u32 dma_fifo_pc;
431 struct mlx5e_tx_mpwqe mpwqe;
432
433 struct mlx5e_cq cq;
434
435 /* read only */
436 struct mlx5_wq_cyc wq;
437 u32 dma_fifo_mask;
438 struct mlx5e_sq_stats *stats;
439 struct {
440 struct mlx5e_sq_dma *dma_fifo;
441 struct mlx5e_skb_fifo skb_fifo;
442 struct mlx5e_tx_wqe_info *wqe_info;
443 } db;
444 void __iomem *uar_map;
445 struct netdev_queue *txq;
446 u32 sqn;
447 u16 stop_room;
448 u8 max_sq_mpw_wqebbs;
449 u8 min_inline_mode;
450 struct device *pdev;
451 __be32 mkey_be;
452 unsigned long state;
453 unsigned int hw_mtu;
454 struct mlx5_clock *clock;
455 struct net_device *netdev;
456 struct mlx5_core_dev *mdev;
457 struct mlx5e_channel *channel;
458 struct mlx5e_priv *priv;
459
460 /* control path */
461 struct mlx5_wq_ctrl wq_ctrl;
462 int ch_ix;
463 int txq_ix;
464 u32 rate_limit;
465 struct work_struct recover_work;
466 struct mlx5e_ptpsq *ptpsq;
467 cqe_ts_to_ns ptp_cyc2time;
468 } ____cacheline_aligned_in_smp;
469
470 union mlx5e_alloc_unit {
471 struct page *page;
472 struct xdp_buff *xsk;
473 };
474
475 /* XDP packets can be transmitted in different ways. On completion, we need to
476 * distinguish between them to clean up things in a proper way.
477 */
478 enum mlx5e_xdp_xmit_mode {
479 /* An xdp_frame was transmitted due to either XDP_REDIRECT from another
480 * device or XDP_TX from an XSK RQ. The frame has to be unmapped and
481 * returned.
482 */
483 MLX5E_XDP_XMIT_MODE_FRAME,
484
485 /* The xdp_frame was created in place as a result of XDP_TX from a
486 * regular RQ. No DMA remapping happened, and the page belongs to us.
487 */
488 MLX5E_XDP_XMIT_MODE_PAGE,
489
490 /* No xdp_frame was created at all, the transmit happened from a UMEM
491 * page. The UMEM Completion Ring producer pointer has to be increased.
492 */
493 MLX5E_XDP_XMIT_MODE_XSK,
494 };
495
496 struct mlx5e_xdp_info {
497 enum mlx5e_xdp_xmit_mode mode;
498 union {
499 struct {
500 struct xdp_frame *xdpf;
501 dma_addr_t dma_addr;
502 } frame;
503 struct {
504 struct mlx5e_rq *rq;
505 struct page *page;
506 } page;
507 };
508 };
509
510 struct mlx5e_xmit_data {
511 dma_addr_t dma_addr;
512 void *data;
513 u32 len;
514 };
515
516 struct mlx5e_xdp_info_fifo {
517 struct mlx5e_xdp_info *xi;
518 u32 *cc;
519 u32 *pc;
520 u32 mask;
521 };
522
523 struct mlx5e_xdpsq;
524 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
525 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
526 struct mlx5e_xmit_data *,
527 struct skb_shared_info *,
528 int);
529
530 struct mlx5e_xdpsq {
531 /* data path */
532
533 /* dirtied @completion */
534 u32 xdpi_fifo_cc;
535 u16 cc;
536
537 /* dirtied @xmit */
538 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
539 u16 pc;
540 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
541 struct mlx5e_tx_mpwqe mpwqe;
542
543 struct mlx5e_cq cq;
544
545 /* read only */
546 struct xsk_buff_pool *xsk_pool;
547 struct mlx5_wq_cyc wq;
548 struct mlx5e_xdpsq_stats *stats;
549 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
550 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
551 struct {
552 struct mlx5e_xdp_wqe_info *wqe_info;
553 struct mlx5e_xdp_info_fifo xdpi_fifo;
554 } db;
555 void __iomem *uar_map;
556 u32 sqn;
557 struct device *pdev;
558 __be32 mkey_be;
559 u16 stop_room;
560 u8 max_sq_mpw_wqebbs;
561 u8 min_inline_mode;
562 unsigned long state;
563 unsigned int hw_mtu;
564
565 /* control path */
566 struct mlx5_wq_ctrl wq_ctrl;
567 struct mlx5e_channel *channel;
568 } ____cacheline_aligned_in_smp;
569
570 struct mlx5e_ktls_resync_resp;
571
572 struct mlx5e_icosq {
573 /* data path */
574 u16 cc;
575 u16 pc;
576
577 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
578 struct mlx5e_cq cq;
579
580 /* write@xmit, read@completion */
581 struct {
582 struct mlx5e_icosq_wqe_info *wqe_info;
583 } db;
584
585 /* read only */
586 struct mlx5_wq_cyc wq;
587 void __iomem *uar_map;
588 u32 sqn;
589 u16 reserved_room;
590 unsigned long state;
591 struct mlx5e_ktls_resync_resp *ktls_resync;
592
593 /* control path */
594 struct mlx5_wq_ctrl wq_ctrl;
595 struct mlx5e_channel *channel;
596
597 struct work_struct recover_work;
598 } ____cacheline_aligned_in_smp;
599
600 struct mlx5e_wqe_frag_info {
601 union mlx5e_alloc_unit *au;
602 u32 offset;
603 bool last_in_page;
604 };
605
606 struct mlx5e_mpw_info {
607 u16 consumed_strides;
608 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_MAX_PAGES_PER_WQE);
609 union mlx5e_alloc_unit alloc_units[];
610 };
611
612 #define MLX5E_MAX_RX_FRAGS 4
613
614 /* a single cache unit is capable to serve one napi call (for non-striding rq)
615 * or a MPWQE (for striding rq).
616 */
617 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_MAX_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
618 MLX5_MPWRQ_MAX_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
619 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
620 struct mlx5e_page_cache {
621 u32 head;
622 u32 tail;
623 struct page *page_cache[MLX5E_CACHE_SIZE];
624 };
625
626 struct mlx5e_rq;
627 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
628 typedef struct sk_buff *
629 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
630 struct mlx5_cqe64 *cqe, u16 cqe_bcnt,
631 u32 head_offset, u32 page_idx);
632 typedef struct sk_buff *
633 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi,
634 struct mlx5_cqe64 *cqe, u32 cqe_bcnt);
635 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
636 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
637 typedef void (*mlx5e_fp_shampo_dealloc_hd)(struct mlx5e_rq*, u16, u16, bool);
638
639 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk);
640 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params);
641
642 enum mlx5e_rq_flag {
643 MLX5E_RQ_FLAG_XDP_XMIT,
644 MLX5E_RQ_FLAG_XDP_REDIRECT,
645 };
646
647 struct mlx5e_rq_frag_info {
648 int frag_size;
649 int frag_stride;
650 };
651
652 struct mlx5e_rq_frags_info {
653 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
654 u8 num_frags;
655 u8 log_num_frags;
656 u8 wqe_bulk;
657 u8 wqe_index_mask;
658 };
659
660 struct mlx5e_dma_info {
661 dma_addr_t addr;
662 struct page *page;
663 };
664
665 struct mlx5e_shampo_hd {
666 u32 mkey;
667 struct mlx5e_dma_info *info;
668 struct page *last_page;
669 u16 hd_per_wq;
670 u16 hd_per_wqe;
671 unsigned long *bitmap;
672 u16 pi;
673 u16 ci;
674 __be32 key;
675 u64 last_addr;
676 };
677
678 struct mlx5e_hw_gro_data {
679 struct sk_buff *skb;
680 struct flow_keys fk;
681 int second_ip_id;
682 };
683
684 enum mlx5e_mpwrq_umr_mode {
685 MLX5E_MPWRQ_UMR_MODE_ALIGNED,
686 MLX5E_MPWRQ_UMR_MODE_UNALIGNED,
687 MLX5E_MPWRQ_UMR_MODE_OVERSIZED,
688 MLX5E_MPWRQ_UMR_MODE_TRIPLE,
689 };
690
691 struct mlx5e_rq {
692 /* data path */
693 union {
694 struct {
695 struct mlx5_wq_cyc wq;
696 struct mlx5e_wqe_frag_info *frags;
697 union mlx5e_alloc_unit *alloc_units;
698 struct mlx5e_rq_frags_info info;
699 mlx5e_fp_skb_from_cqe skb_from_cqe;
700 } wqe;
701 struct {
702 struct mlx5_wq_ll wq;
703 struct mlx5e_umr_wqe umr_wqe;
704 struct mlx5e_mpw_info *info;
705 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
706 __be32 umr_mkey_be;
707 u16 num_strides;
708 u16 actual_wq_head;
709 u8 log_stride_sz;
710 u8 umr_in_progress;
711 u8 umr_last_bulk;
712 u8 umr_completed;
713 u8 min_wqe_bulk;
714 u8 page_shift;
715 u8 pages_per_wqe;
716 u8 umr_wqebbs;
717 u8 mtts_per_wqe;
718 u8 umr_mode;
719 struct mlx5e_shampo_hd *shampo;
720 } mpwqe;
721 };
722 struct {
723 u16 headroom;
724 u32 frame0_sz;
725 u8 map_dir; /* dma map direction */
726 } buff;
727
728 struct device *pdev;
729 struct net_device *netdev;
730 struct mlx5e_rq_stats *stats;
731 struct mlx5e_cq cq;
732 struct mlx5e_cq_decomp cqd;
733 struct mlx5e_page_cache page_cache;
734 struct hwtstamp_config *tstamp;
735 struct mlx5_clock *clock;
736 struct mlx5e_icosq *icosq;
737 struct mlx5e_priv *priv;
738
739 struct mlx5e_hw_gro_data *hw_gro_data;
740
741 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
742 mlx5e_fp_post_rx_wqes post_wqes;
743 mlx5e_fp_dealloc_wqe dealloc_wqe;
744
745 unsigned long state;
746 int ix;
747 unsigned int hw_mtu;
748
749 struct dim dim; /* Dynamic Interrupt Moderation */
750
751 /* XDP */
752 struct bpf_prog __rcu *xdp_prog;
753 struct mlx5e_xdpsq *xdpsq;
754 DECLARE_BITMAP(flags, 8);
755 struct page_pool *page_pool;
756
757 /* AF_XDP zero-copy */
758 struct xsk_buff_pool *xsk_pool;
759
760 struct work_struct recover_work;
761
762 /* control */
763 struct mlx5_wq_ctrl wq_ctrl;
764 __be32 mkey_be;
765 u8 wq_type;
766 u32 rqn;
767 struct mlx5_core_dev *mdev;
768 struct mlx5e_channel *channel;
769 struct mlx5e_dma_info wqe_overflow;
770
771 /* XDP read-mostly */
772 struct xdp_rxq_info xdp_rxq;
773 cqe_ts_to_ns ptp_cyc2time;
774 } ____cacheline_aligned_in_smp;
775
776 enum mlx5e_channel_state {
777 MLX5E_CHANNEL_STATE_XSK,
778 MLX5E_CHANNEL_NUM_STATES
779 };
780
781 struct mlx5e_channel {
782 /* data path */
783 struct mlx5e_rq rq;
784 struct mlx5e_xdpsq rq_xdpsq;
785 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
786 struct mlx5e_icosq icosq; /* internal control operations */
787 struct mlx5e_txqsq __rcu * __rcu *qos_sqs;
788 bool xdp;
789 struct napi_struct napi;
790 struct device *pdev;
791 struct net_device *netdev;
792 __be32 mkey_be;
793 u16 qos_sqs_size;
794 u8 num_tc;
795 u8 lag_port;
796
797 /* XDP_REDIRECT */
798 struct mlx5e_xdpsq xdpsq;
799
800 /* AF_XDP zero-copy */
801 struct mlx5e_rq xskrq;
802 struct mlx5e_xdpsq xsksq;
803
804 /* Async ICOSQ */
805 struct mlx5e_icosq async_icosq;
806 /* async_icosq can be accessed from any CPU - the spinlock protects it. */
807 spinlock_t async_icosq_lock;
808
809 /* data path - accessed per napi poll */
810 const struct cpumask *aff_mask;
811 struct mlx5e_ch_stats *stats;
812
813 /* control */
814 struct mlx5e_priv *priv;
815 struct mlx5_core_dev *mdev;
816 struct hwtstamp_config *tstamp;
817 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
818 int ix;
819 int cpu;
820 /* Sync between icosq recovery and XSK enable/disable. */
821 struct mutex icosq_recovery_lock;
822 };
823
824 struct mlx5e_ptp;
825
826 struct mlx5e_channels {
827 struct mlx5e_channel **c;
828 struct mlx5e_ptp *ptp;
829 unsigned int num;
830 struct mlx5e_params params;
831 };
832
833 struct mlx5e_channel_stats {
834 struct mlx5e_ch_stats ch;
835 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
836 struct mlx5e_rq_stats rq;
837 struct mlx5e_rq_stats xskrq;
838 struct mlx5e_xdpsq_stats rq_xdpsq;
839 struct mlx5e_xdpsq_stats xdpsq;
840 struct mlx5e_xdpsq_stats xsksq;
841 } ____cacheline_aligned_in_smp;
842
843 struct mlx5e_ptp_stats {
844 struct mlx5e_ch_stats ch;
845 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
846 struct mlx5e_ptp_cq_stats cq[MLX5E_MAX_NUM_TC];
847 struct mlx5e_rq_stats rq;
848 } ____cacheline_aligned_in_smp;
849
850 enum {
851 MLX5E_STATE_OPENED,
852 MLX5E_STATE_DESTROYING,
853 MLX5E_STATE_XDP_TX_ENABLED,
854 MLX5E_STATE_XDP_ACTIVE,
855 };
856
857 struct mlx5e_modify_sq_param {
858 int curr_state;
859 int next_state;
860 int rl_update;
861 int rl_index;
862 bool qos_update;
863 u16 qos_queue_group_id;
864 };
865
866 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
867 struct mlx5e_hv_vhca_stats_agent {
868 struct mlx5_hv_vhca_agent *agent;
869 struct delayed_work work;
870 u16 delay;
871 void *buf;
872 };
873 #endif
874
875 struct mlx5e_xsk {
876 /* XSK buffer pools are stored separately from channels,
877 * because we don't want to lose them when channels are
878 * recreated. The kernel also stores buffer pool, but it doesn't
879 * distinguish between zero-copy and non-zero-copy UMEMs, so
880 * rely on our mechanism.
881 */
882 struct xsk_buff_pool **pools;
883 u16 refcnt;
884 bool ever_used;
885 };
886
887 /* Temporary storage for variables that are allocated when struct mlx5e_priv is
888 * initialized, and used where we can't allocate them because that functions
889 * must not fail. Use with care and make sure the same variable is not used
890 * simultaneously by multiple users.
891 */
892 struct mlx5e_scratchpad {
893 cpumask_var_t cpumask;
894 };
895
896 struct mlx5e_trap;
897 struct mlx5e_htb;
898
899 struct mlx5e_priv {
900 /* priv data path fields - start */
901 struct mlx5e_selq selq;
902 struct mlx5e_txqsq **txq2sq;
903 #ifdef CONFIG_MLX5_CORE_EN_DCB
904 struct mlx5e_dcbx_dp dcbx_dp;
905 #endif
906 /* priv data path fields - end */
907
908 u32 msglevel;
909 unsigned long state;
910 struct mutex state_lock; /* Protects Interface state */
911 struct mlx5e_rq drop_rq;
912
913 struct mlx5e_channels channels;
914 u32 tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC];
915 struct mlx5e_rx_res *rx_res;
916 u32 *tx_rates;
917
918 struct mlx5e_flow_steering *fs;
919
920 struct workqueue_struct *wq;
921 struct work_struct update_carrier_work;
922 struct work_struct set_rx_mode_work;
923 struct work_struct tx_timeout_work;
924 struct work_struct update_stats_work;
925 struct work_struct monitor_counters_work;
926 struct mlx5_nb monitor_counters_nb;
927
928 struct mlx5_core_dev *mdev;
929 struct net_device *netdev;
930 struct mlx5e_trap *en_trap;
931 struct mlx5e_stats stats;
932 struct mlx5e_channel_stats **channel_stats;
933 struct mlx5e_channel_stats trap_stats;
934 struct mlx5e_ptp_stats ptp_stats;
935 struct mlx5e_sq_stats **htb_qos_sq_stats;
936 u16 htb_max_qos_sqs;
937 u16 stats_nch;
938 u16 max_nch;
939 u8 max_opened_tc;
940 bool tx_ptp_opened;
941 bool rx_ptp_opened;
942 struct hwtstamp_config tstamp;
943 u16 q_counter;
944 u16 drop_rq_q_counter;
945 struct notifier_block events_nb;
946 struct notifier_block blocking_events_nb;
947
948 struct udp_tunnel_nic_info nic_info;
949 #ifdef CONFIG_MLX5_CORE_EN_DCB
950 struct mlx5e_dcbx dcbx;
951 #endif
952
953 const struct mlx5e_profile *profile;
954 void *ppriv;
955 #ifdef CONFIG_MLX5_EN_MACSEC
956 struct mlx5e_macsec *macsec;
957 #endif
958 #ifdef CONFIG_MLX5_EN_IPSEC
959 struct mlx5e_ipsec *ipsec;
960 #endif
961 #ifdef CONFIG_MLX5_EN_TLS
962 struct mlx5e_tls *tls;
963 #endif
964 struct devlink_health_reporter *tx_reporter;
965 struct devlink_health_reporter *rx_reporter;
966 struct mlx5e_xsk xsk;
967 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
968 struct mlx5e_hv_vhca_stats_agent stats_agent;
969 #endif
970 struct mlx5e_scratchpad scratchpad;
971 struct mlx5e_htb *htb;
972 struct mlx5e_mqprio_rl *mqprio_rl;
973 struct dentry *dfs_root;
974 };
975
976 struct mlx5e_dev {
977 struct mlx5e_priv *priv;
978 struct devlink_port dl_port;
979 };
980
981 struct mlx5e_rx_handlers {
982 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
983 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
984 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe_shampo;
985 };
986
987 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic;
988
989 enum mlx5e_profile_feature {
990 MLX5E_PROFILE_FEATURE_PTP_RX,
991 MLX5E_PROFILE_FEATURE_PTP_TX,
992 MLX5E_PROFILE_FEATURE_QOS_HTB,
993 MLX5E_PROFILE_FEATURE_FS_VLAN,
994 MLX5E_PROFILE_FEATURE_FS_TC,
995 };
996
997 struct mlx5e_profile {
998 int (*init)(struct mlx5_core_dev *mdev,
999 struct net_device *netdev);
1000 void (*cleanup)(struct mlx5e_priv *priv);
1001 int (*init_rx)(struct mlx5e_priv *priv);
1002 void (*cleanup_rx)(struct mlx5e_priv *priv);
1003 int (*init_tx)(struct mlx5e_priv *priv);
1004 void (*cleanup_tx)(struct mlx5e_priv *priv);
1005 void (*enable)(struct mlx5e_priv *priv);
1006 void (*disable)(struct mlx5e_priv *priv);
1007 int (*update_rx)(struct mlx5e_priv *priv);
1008 void (*update_stats)(struct mlx5e_priv *priv);
1009 void (*update_carrier)(struct mlx5e_priv *priv);
1010 int (*max_nch_limit)(struct mlx5_core_dev *mdev);
1011 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv);
1012 mlx5e_stats_grp_t *stats_grps;
1013 const struct mlx5e_rx_handlers *rx_handlers;
1014 int max_tc;
1015 u32 features;
1016 };
1017
1018 #define mlx5e_profile_feature_cap(profile, feature) \
1019 ((profile)->features & BIT(MLX5E_PROFILE_FEATURE_##feature))
1020
1021 void mlx5e_build_ptys2ethtool_map(void);
1022
1023 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift,
1024 enum mlx5e_mpwrq_umr_mode umr_mode);
1025
1026 void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq, u16 len, u16 start, bool close);
1027 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
1028 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
1029
1030 int mlx5e_self_test_num(struct mlx5e_priv *priv);
1031 int mlx5e_self_test_fill_strings(struct mlx5e_priv *priv, u8 *data);
1032 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
1033 u64 *buf);
1034 void mlx5e_set_rx_mode_work(struct work_struct *work);
1035
1036 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
1037 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
1038 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter);
1039
1040 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
1041 u16 vid);
1042 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
1043 u16 vid);
1044 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
1045
1046 struct mlx5e_xsk_param;
1047
1048 struct mlx5e_rq_param;
1049 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1050 struct mlx5e_xsk_param *xsk, int node,
1051 struct mlx5e_rq *rq);
1052 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
1053 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
1054 void mlx5e_close_rq(struct mlx5e_rq *rq);
1055 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param);
1056 void mlx5e_destroy_rq(struct mlx5e_rq *rq);
1057
1058 struct mlx5e_sq_param;
1059 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1060 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1061 struct mlx5e_xdpsq *sq, bool is_redirect);
1062 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
1063
1064 struct mlx5e_create_cq_param {
1065 struct napi_struct *napi;
1066 struct mlx5e_ch_stats *ch_stats;
1067 int node;
1068 int ix;
1069 };
1070
1071 struct mlx5e_cq_param;
1072 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1073 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1074 struct mlx5e_cq *cq);
1075 void mlx5e_close_cq(struct mlx5e_cq *cq);
1076
1077 int mlx5e_open_locked(struct net_device *netdev);
1078 int mlx5e_close_locked(struct net_device *netdev);
1079
1080 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c);
1081 void mlx5e_trigger_napi_sched(struct napi_struct *napi);
1082
1083 int mlx5e_open_channels(struct mlx5e_priv *priv,
1084 struct mlx5e_channels *chs);
1085 void mlx5e_close_channels(struct mlx5e_channels *chs);
1086
1087 /* Function pointer to be used to modify HW or kernel settings while
1088 * switching channels
1089 */
1090 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context);
1091 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \
1092 int fn##_ctx(struct mlx5e_priv *priv, void *context) \
1093 { \
1094 return fn(priv); \
1095 }
1096 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
1097 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
1098 struct mlx5e_params *new_params,
1099 mlx5e_fp_preactivate preactivate,
1100 void *context, bool reset);
1101 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv);
1102 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context);
1103 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
1104 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
1105 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx);
1106
1107 int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state);
1108 void mlx5e_activate_rq(struct mlx5e_rq *rq);
1109 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
1110 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq);
1111 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);
1112
1113 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1114 struct mlx5e_modify_sq_param *p);
1115 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1116 struct mlx5e_params *params, struct mlx5e_sq_param *param,
1117 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1118 struct mlx5e_sq_stats *sq_stats);
1119 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
1120 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq);
1121 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq);
1122 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
1123 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa);
1124 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq);
1125 struct mlx5e_create_sq_param;
1126 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1127 struct mlx5e_sq_param *param,
1128 struct mlx5e_create_sq_param *csp,
1129 u16 qos_queue_group_id,
1130 u32 *sqn);
1131 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1132 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq);
1133
mlx5_tx_swp_supported(struct mlx5_core_dev * mdev)1134 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
1135 {
1136 return MLX5_CAP_ETH(mdev, swp) &&
1137 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
1138 }
1139
1140 extern const struct ethtool_ops mlx5e_ethtool_ops;
1141
1142 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey);
1143 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1144 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1145 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
1146 bool enable_mc_lb);
1147 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc);
1148
1149 /* common netdev helpers */
1150 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
1151 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
1152 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1153 struct mlx5e_rq *drop_rq);
1154 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
1155
1156 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1157 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1158
1159 int mlx5e_create_tises(struct mlx5e_priv *priv);
1160 void mlx5e_destroy_tises(struct mlx5e_priv *priv);
1161 int mlx5e_update_nic_rx(struct mlx5e_priv *priv);
1162 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1163 int mlx5e_close(struct net_device *netdev);
1164 int mlx5e_open(struct net_device *netdev);
1165
1166 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1167
1168 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1169 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context);
1170 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1171 mlx5e_fp_preactivate preactivate);
1172 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv);
1173
1174 /* ethtool helpers */
1175 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1176 struct ethtool_drvinfo *drvinfo);
1177 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1178 uint32_t stringset, uint8_t *data);
1179 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1180 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1181 struct ethtool_stats *stats, u64 *data);
1182 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1183 struct ethtool_ringparam *param,
1184 struct kernel_ethtool_ringparam *kernel_param);
1185 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1186 struct ethtool_ringparam *param);
1187 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1188 struct ethtool_channels *ch);
1189 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1190 struct ethtool_channels *ch);
1191 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1192 struct ethtool_coalesce *coal,
1193 struct kernel_ethtool_coalesce *kernel_coal);
1194 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1195 struct ethtool_coalesce *coal,
1196 struct kernel_ethtool_coalesce *kernel_coal,
1197 struct netlink_ext_ack *extack);
1198 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1199 struct ethtool_link_ksettings *link_ksettings);
1200 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1201 const struct ethtool_link_ksettings *link_ksettings);
1202 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc);
1203 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,
1204 const u8 hfunc);
1205 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
1206 u32 *rule_locs);
1207 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd);
1208 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1209 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1210 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1211 struct ethtool_ts_info *info);
1212 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1213 struct ethtool_flash *flash);
1214 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1215 struct ethtool_pauseparam *pauseparam);
1216 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1217 struct ethtool_pauseparam *pauseparam);
1218
1219 /* mlx5e generic netdev management API */
1220 static inline bool
mlx5e_tx_mpwqe_supported(struct mlx5_core_dev * mdev)1221 mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev)
1222 {
1223 return !is_kdump_kernel() &&
1224 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe);
1225 }
1226
1227 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev);
1228 int mlx5e_priv_init(struct mlx5e_priv *priv,
1229 const struct mlx5e_profile *profile,
1230 struct net_device *netdev,
1231 struct mlx5_core_dev *mdev);
1232 void mlx5e_priv_cleanup(struct mlx5e_priv *priv);
1233 struct net_device *
1234 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile);
1235 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1236 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1237 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1238 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
1239 const struct mlx5e_profile *new_profile, void *new_ppriv);
1240 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv);
1241 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1242 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu);
1243 void mlx5e_rx_dim_work(struct work_struct *work);
1244 void mlx5e_tx_dim_work(struct work_struct *work);
1245
1246 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1247 struct net_device *netdev,
1248 netdev_features_t features);
1249 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1250 #ifdef CONFIG_MLX5_ESWITCH
1251 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1252 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1253 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1254 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1255 #endif
1256 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey);
1257 #endif /* __MLX5_EN_H__ */
1258