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Searched refs:mmIH_RB_BASE (Results 1 – 16 of 16) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/include/asic_reg/oss/
A Doss_1_0_d.h230 #define mmIH_RB_BASE 0x0F81 macro
A Dosssys_4_0_1_offset.h122 #define mmIH_RB_BASE macro
A Dosssys_4_0_offset.h122 #define mmIH_RB_BASE macro
A Dosssys_4_2_0_offset.h124 #define mmIH_RB_BASE macro
A Dosssys_5_0_0_offset.h122 #define mmIH_RB_BASE macro
A Doss_2_4_d.h44 #define mmIH_RB_BASE 0xe31 macro
A Doss_3_0_1_d.h44 #define mmIH_RB_BASE 0xe31 macro
A Doss_2_0_d.h44 #define mmIH_RB_BASE 0xf81 macro
A Doss_3_0_d.h44 #define mmIH_RB_BASE 0xe31 macro
/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Dcik_ih.c126 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in cik_ih_irq_init()
A Dcz_ih.c127 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in cz_ih_irq_init()
A Diceland_ih.c127 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in iceland_ih_irq_init()
A Dtonga_ih.c123 WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8); in tonga_ih_irq_init()
A Dvega10_ih.c53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in vega10_ih_init_register_offset()
A Dnavi10_ih.c55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in navi10_ih_init_register_offset()
A Dvega20_ih.c56 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in vega20_ih_init_register_offset()

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