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Searched refs:mmPSOC_CPU_PLL_DIV_SEL_2 (Results 1 – 2 of 2) sorted by relevance

/linux-6.3-rc2/drivers/accel/habanalabs/include/gaudi/asic_reg/
A Dpsoc_cpu_pll_regs.h64 #define mmPSOC_CPU_PLL_DIV_SEL_2 0xC70288 macro
/linux-6.3-rc2/drivers/accel/habanalabs/gaudi/
A Dgaudi.c925 div_sel = RREG32(mmPSOC_CPU_PLL_DIV_SEL_2); in gaudi_fetch_psoc_frequency()

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