/linux-6.3-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
A D | uvd_5_0_d.h | 42 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x3c5f macro
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A D | uvd_6_0_d.h | 53 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x3c5f macro
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A D | uvd_7_0_offset.h | 108 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW … macro
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/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/ |
A D | vcn_v2_0.c | 339 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_0_mc_resume() 346 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_0_mc_resume() 394 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_0_mc_resume_dpg_mode() 403 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode() 412 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_0_mc_resume_dpg_mode() 1891 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_0_start_sriov() 1901 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_0_start_sriov()
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A D | vcn_v2_5.c | 407 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_5_mc_resume() 414 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_5_mc_resume() 460 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode() 469 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode() 478 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode() 1231 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_5_sriov_start() 1243 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_5_sriov_start()
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A D | vcn_v3_0.c | 453 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v3_0_mc_resume() 460 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v3_0_mc_resume() 505 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode() 514 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode() 523 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode() 1336 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v3_0_start_sriov() 1347 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v3_0_start_sriov()
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A D | uvd_v7_0.c | 678 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v7_0_mc_resume() 689 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v7_0_mc_resume() 823 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in uvd_v7_0_sriov_start() 831 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in uvd_v7_0_sriov_start()
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A D | vcn_v1_0.c | 310 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_spg_mode() 317 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_spg_mode() 377 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_dpg_mode() 387 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_dpg_mode()
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A D | uvd_v5_0.c | 282 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v5_0_mc_resume()
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A D | uvd_v6_0.c | 606 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v6_0_mc_resume()
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/linux-6.3-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
A D | vcn_1_0_offset.h | 234 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW … macro
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A D | vcn_2_5_offset.h | 865 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW … macro
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A D | vcn_2_0_0_offset.h | 944 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW … macro
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A D | vcn_3_0_0_offset.h | 1283 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW … macro
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