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Searched refs:mmUVD_POWER_STATUS (Results 1 – 17 of 17) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Dvcn_v1_0.c731 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_1_0_disable_static_power_gating()
736 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_1_0_disable_static_power_gating()
745 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_1_0_enable_static_power_gating()
748 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_1_0_enable_static_power_gating()
973 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); in vcn_v1_0_start_dpg_mode()
976 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); in vcn_v1_0_start_dpg_mode()
1169 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, in vcn_v1_0_stop_dpg_mode()
1186 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, in vcn_v1_0_stop_dpg_mode()
1261 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, in vcn_v1_0_pause_dpg_mode()
1295 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2); in vcn_v1_0_pause_dpg_mode()
[all …]
A Dvcn_v2_0.c742 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_v2_0_disable_static_power_gating()
748 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_v2_0_disable_static_power_gating()
760 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_v2_0_enable_static_power_gating()
763 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_v2_0_enable_static_power_gating()
802 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); in vcn_v2_0_start_dpg_mode()
805 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); in vcn_v2_0_start_dpg_mode()
896 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), in vcn_v2_0_start_dpg_mode()
925 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), in vcn_v2_0_start_dpg_mode()
1110 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, in vcn_v2_0_stop_dpg_mode()
1123 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, in vcn_v2_0_stop_dpg_mode()
[all …]
A Dvcn_v2_5.c808 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, in vcn_v2_5_start_dpg_mode()
811 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); in vcn_v2_5_start_dpg_mode()
814 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); in vcn_v2_5_start_dpg_mode()
912 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode()
941 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode()
965 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0, in vcn_v2_5_start()
1341 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1354 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1421 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), in vcn_v2_5_stop()
1492 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, in vcn_v2_5_pause_dpg_mode()
[all …]
A Dvcn_v3_0.c634 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); in vcn_v3_0_disable_static_power_gating()
640 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); in vcn_v3_0_disable_static_power_gating()
649 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); in vcn_v3_0_enable_static_power_gating()
652 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); in vcn_v3_0_enable_static_power_gating()
950 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); in vcn_v3_0_start_dpg_mode()
953 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); in vcn_v3_0_start_dpg_mode()
1053 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v3_0_start_dpg_mode()
1088 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v3_0_start_dpg_mode()
1499 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v3_0_stop_dpg_mode()
1512 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v3_0_stop_dpg_mode()
[all …]
A Duvd_v5_0.c324 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); in uvd_v5_0_start()
A Duvd_v6_0.c729 WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); in uvd_v6_0_start()
1483 WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); in uvd_v6_0_set_powergating_state()
A Duvd_v7_0.c960 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0, in uvd_v7_0_start()
1762 WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
/linux-6.3-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
A Duvd_4_0_d.h65 #define mmUVD_POWER_STATUS 0x38FC macro
A Duvd_4_2_d.h91 #define mmUVD_POWER_STATUS 0x38fc macro
A Duvd_3_1_d.h93 #define mmUVD_POWER_STATUS 0x38fc macro
A Duvd_5_0_d.h103 #define mmUVD_POWER_STATUS 0x38c4 macro
A Duvd_6_0_d.h119 #define mmUVD_POWER_STATUS 0x38c4 macro
A Duvd_7_0_offset.h28 #define mmUVD_POWER_STATUS … macro
/linux-6.3-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/
A Dvcn_1_0_offset.h32 #define mmUVD_POWER_STATUS … macro
A Dvcn_2_5_offset.h399 #define mmUVD_POWER_STATUS … macro
A Dvcn_2_0_0_offset.h384 #define mmUVD_POWER_STATUS … macro
A Dvcn_3_0_0_offset.h667 #define mmUVD_POWER_STATUS … macro

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