Searched refs:mmUVD_RB_RPTR (Results 1 – 12 of 12) sorted by relevance
| /linux-6.3-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| A D | uvd_6_0_d.h | 47 #define mmUVD_RB_RPTR 0x3c29 macro
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| A D | uvd_7_0_offset.h | 100 #define mmUVD_RB_RPTR … macro
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| /linux-6.3-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| A D | vcn_1_0_offset.h | 222 #define mmUVD_RB_RPTR … macro
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| A D | vcn_2_5_offset.h | 557 #define mmUVD_RB_RPTR … macro
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| A D | vcn_2_0_0_offset.h | 934 #define mmUVD_RB_RPTR … macro
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| A D | vcn_3_0_0_offset.h | 887 #define mmUVD_RB_RPTR … macro
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| /linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/ |
| A D | vcn_v1_0.c | 943 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
1175 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v1_0_stop_dpg_mode()
1248 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_pause_dpg_mode()
1591 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); in vcn_v1_0_enc_ring_get_rptr()
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| A D | vcn_v2_0.c | 1084 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1115 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_0_stop_dpg_mode()
1241 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode()
1554 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); in vcn_v2_0_enc_ring_get_rptr()
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| A D | vcn_v2_5.c | 1120 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1346 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1474 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode()
1631 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); in vcn_v2_5_enc_ring_get_rptr()
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| A D | vcn_v3_0.c | 1261 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_start()
1504 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1640 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_pause_dpg_mode()
1942 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); in vcn_v3_0_enc_ring_get_rptr()
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| A D | uvd_v6_0.c | 96 return RREG32(mmUVD_RB_RPTR); in uvd_v6_0_enc_ring_get_rptr()
863 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
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| A D | uvd_v7_0.c | 90 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); in uvd_v7_0_enc_ring_get_rptr()
1112 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_start()
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