1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016 MediaTek Inc.
4 * Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
5 * Rick Chang <rick.chang@mediatek.com>
6 */
7
8 #include <linux/clk.h>
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/slab.h>
18 #include <media/media-device.h>
19 #include <media/videobuf2-core.h>
20 #include <media/videobuf2-v4l2.h>
21 #include <media/v4l2-mem2mem.h>
22 #include <media/v4l2-dev.h>
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-fh.h>
25 #include <media/v4l2-event.h>
26
27 #include "mtk_jpeg_core.h"
28 #include "mtk_jpeg_dec_hw.h"
29
30 #define MTK_JPEG_DUNUM_MASK(val) (((val) - 1) & 0x3)
31
32 enum mtk_jpeg_color {
33 MTK_JPEG_COLOR_420 = 0x00221111,
34 MTK_JPEG_COLOR_422 = 0x00211111,
35 MTK_JPEG_COLOR_444 = 0x00111111,
36 MTK_JPEG_COLOR_422V = 0x00121111,
37 MTK_JPEG_COLOR_422X2 = 0x00412121,
38 MTK_JPEG_COLOR_422VX2 = 0x00222121,
39 MTK_JPEG_COLOR_400 = 0x00110000
40 };
41
42 #if defined(CONFIG_OF)
43 static const struct of_device_id mtk_jpegdec_hw_ids[] = {
44 {
45 .compatible = "mediatek,mt8195-jpgdec-hw",
46 },
47 {},
48 };
49 MODULE_DEVICE_TABLE(of, mtk_jpegdec_hw_ids);
50 #endif
51
mtk_jpeg_verify_align(u32 val,int align,u32 reg)52 static inline int mtk_jpeg_verify_align(u32 val, int align, u32 reg)
53 {
54 if (val & (align - 1)) {
55 pr_err("mtk-jpeg: write reg %x without %d align\n", reg, align);
56 return -1;
57 }
58
59 return 0;
60 }
61
mtk_jpeg_decide_format(struct mtk_jpeg_dec_param * param)62 static int mtk_jpeg_decide_format(struct mtk_jpeg_dec_param *param)
63 {
64 param->src_color = (param->sampling_w[0] << 20) |
65 (param->sampling_h[0] << 16) |
66 (param->sampling_w[1] << 12) |
67 (param->sampling_h[1] << 8) |
68 (param->sampling_w[2] << 4) |
69 (param->sampling_h[2]);
70
71 param->uv_brz_w = 0;
72 switch (param->src_color) {
73 case MTK_JPEG_COLOR_444:
74 param->uv_brz_w = 1;
75 param->dst_fourcc = V4L2_PIX_FMT_YUV422M;
76 break;
77 case MTK_JPEG_COLOR_422X2:
78 case MTK_JPEG_COLOR_422:
79 param->dst_fourcc = V4L2_PIX_FMT_YUV422M;
80 break;
81 case MTK_JPEG_COLOR_422V:
82 case MTK_JPEG_COLOR_422VX2:
83 param->uv_brz_w = 1;
84 param->dst_fourcc = V4L2_PIX_FMT_YUV420M;
85 break;
86 case MTK_JPEG_COLOR_420:
87 param->dst_fourcc = V4L2_PIX_FMT_YUV420M;
88 break;
89 case MTK_JPEG_COLOR_400:
90 param->dst_fourcc = V4L2_PIX_FMT_GREY;
91 break;
92 default:
93 param->dst_fourcc = 0;
94 return -1;
95 }
96
97 return 0;
98 }
99
mtk_jpeg_calc_mcu(struct mtk_jpeg_dec_param * param)100 static void mtk_jpeg_calc_mcu(struct mtk_jpeg_dec_param *param)
101 {
102 u32 factor_w, factor_h;
103 u32 i, comp, blk;
104
105 factor_w = 2 + param->sampling_w[0];
106 factor_h = 2 + param->sampling_h[0];
107 param->mcu_w = (param->pic_w + (1 << factor_w) - 1) >> factor_w;
108 param->mcu_h = (param->pic_h + (1 << factor_h) - 1) >> factor_h;
109 param->total_mcu = param->mcu_w * param->mcu_h;
110 param->unit_num = ((param->pic_w + 7) >> 3) * ((param->pic_h + 7) >> 3);
111 param->blk_num = 0;
112 for (i = 0; i < MTK_JPEG_COMP_MAX; i++) {
113 param->blk_comp[i] = 0;
114 if (i >= param->comp_num)
115 continue;
116 param->blk_comp[i] = param->sampling_w[i] *
117 param->sampling_h[i];
118 param->blk_num += param->blk_comp[i];
119 }
120
121 param->membership = 0;
122 for (i = 0, blk = 0, comp = 0; i < MTK_JPEG_BLOCK_MAX; i++) {
123 if (i < param->blk_num && comp < param->comp_num) {
124 u32 tmp;
125
126 tmp = (0x04 + (comp & 0x3));
127 param->membership |= tmp << (i * 3);
128 if (++blk == param->blk_comp[comp]) {
129 comp++;
130 blk = 0;
131 }
132 } else {
133 param->membership |= 7 << (i * 3);
134 }
135 }
136 }
137
mtk_jpeg_calc_dma_group(struct mtk_jpeg_dec_param * param)138 static void mtk_jpeg_calc_dma_group(struct mtk_jpeg_dec_param *param)
139 {
140 u32 factor_mcu = 3;
141
142 if (param->src_color == MTK_JPEG_COLOR_444 &&
143 param->dst_fourcc == V4L2_PIX_FMT_YUV422M)
144 factor_mcu = 4;
145 else if (param->src_color == MTK_JPEG_COLOR_422V &&
146 param->dst_fourcc == V4L2_PIX_FMT_YUV420M)
147 factor_mcu = 4;
148 else if (param->src_color == MTK_JPEG_COLOR_422X2 &&
149 param->dst_fourcc == V4L2_PIX_FMT_YUV422M)
150 factor_mcu = 2;
151 else if (param->src_color == MTK_JPEG_COLOR_400 ||
152 (param->src_color & 0x0FFFF) == 0)
153 factor_mcu = 4;
154
155 param->dma_mcu = 1 << factor_mcu;
156 param->dma_group = param->mcu_w / param->dma_mcu;
157 param->dma_last_mcu = param->mcu_w % param->dma_mcu;
158 if (param->dma_last_mcu)
159 param->dma_group++;
160 else
161 param->dma_last_mcu = param->dma_mcu;
162 }
163
mtk_jpeg_calc_dst_size(struct mtk_jpeg_dec_param * param)164 static int mtk_jpeg_calc_dst_size(struct mtk_jpeg_dec_param *param)
165 {
166 u32 i, padding_w;
167 u32 ds_row_h[3];
168 u32 brz_w[3];
169
170 brz_w[0] = 0;
171 brz_w[1] = param->uv_brz_w;
172 brz_w[2] = brz_w[1];
173
174 for (i = 0; i < param->comp_num; i++) {
175 if (brz_w[i] > 3)
176 return -1;
177
178 padding_w = param->mcu_w * MTK_JPEG_DCTSIZE *
179 param->sampling_w[i];
180 /* output format is 420/422 */
181 param->comp_w[i] = padding_w >> brz_w[i];
182 param->comp_w[i] = round_up(param->comp_w[i],
183 MTK_JPEG_DCTSIZE);
184 param->img_stride[i] = i ? round_up(param->comp_w[i], 16)
185 : round_up(param->comp_w[i], 32);
186 ds_row_h[i] = (MTK_JPEG_DCTSIZE * param->sampling_h[i]);
187 }
188 param->dec_w = param->img_stride[0];
189 param->dec_h = ds_row_h[0] * param->mcu_h;
190
191 for (i = 0; i < MTK_JPEG_COMP_MAX; i++) {
192 /* They must be equal in frame mode. */
193 param->mem_stride[i] = param->img_stride[i];
194 param->comp_size[i] = param->mem_stride[i] * ds_row_h[i] *
195 param->mcu_h;
196 }
197
198 param->y_size = param->comp_size[0];
199 param->uv_size = param->comp_size[1];
200 param->dec_size = param->y_size + (param->uv_size << 1);
201
202 return 0;
203 }
204
mtk_jpeg_dec_fill_param(struct mtk_jpeg_dec_param * param)205 int mtk_jpeg_dec_fill_param(struct mtk_jpeg_dec_param *param)
206 {
207 if (mtk_jpeg_decide_format(param))
208 return -1;
209
210 mtk_jpeg_calc_mcu(param);
211 mtk_jpeg_calc_dma_group(param);
212 if (mtk_jpeg_calc_dst_size(param))
213 return -2;
214
215 return 0;
216 }
217 EXPORT_SYMBOL_GPL(mtk_jpeg_dec_fill_param);
218
mtk_jpeg_dec_get_int_status(void __iomem * base)219 u32 mtk_jpeg_dec_get_int_status(void __iomem *base)
220 {
221 u32 ret;
222
223 ret = readl(base + JPGDEC_REG_INTERRUPT_STATUS) & BIT_INQST_MASK_ALLIRQ;
224 if (ret)
225 writel(ret, base + JPGDEC_REG_INTERRUPT_STATUS);
226
227 return ret;
228 }
229 EXPORT_SYMBOL_GPL(mtk_jpeg_dec_get_int_status);
230
mtk_jpeg_dec_enum_result(u32 irq_result)231 u32 mtk_jpeg_dec_enum_result(u32 irq_result)
232 {
233 if (irq_result & BIT_INQST_MASK_EOF)
234 return MTK_JPEG_DEC_RESULT_EOF_DONE;
235 if (irq_result & BIT_INQST_MASK_PAUSE)
236 return MTK_JPEG_DEC_RESULT_PAUSE;
237 if (irq_result & BIT_INQST_MASK_UNDERFLOW)
238 return MTK_JPEG_DEC_RESULT_UNDERFLOW;
239 if (irq_result & BIT_INQST_MASK_OVERFLOW)
240 return MTK_JPEG_DEC_RESULT_OVERFLOW;
241 if (irq_result & BIT_INQST_MASK_ERROR_BS)
242 return MTK_JPEG_DEC_RESULT_ERROR_BS;
243
244 return MTK_JPEG_DEC_RESULT_ERROR_UNKNOWN;
245 }
246 EXPORT_SYMBOL_GPL(mtk_jpeg_dec_enum_result);
247
mtk_jpeg_dec_start(void __iomem * base)248 void mtk_jpeg_dec_start(void __iomem *base)
249 {
250 writel(0, base + JPGDEC_REG_TRIG);
251 }
252 EXPORT_SYMBOL_GPL(mtk_jpeg_dec_start);
253
mtk_jpeg_dec_soft_reset(void __iomem * base)254 static void mtk_jpeg_dec_soft_reset(void __iomem *base)
255 {
256 writel(0x0000FFFF, base + JPGDEC_REG_INTERRUPT_STATUS);
257 writel(0x00, base + JPGDEC_REG_RESET);
258 writel(0x01, base + JPGDEC_REG_RESET);
259 }
260
mtk_jpeg_dec_hard_reset(void __iomem * base)261 static void mtk_jpeg_dec_hard_reset(void __iomem *base)
262 {
263 writel(0x00, base + JPGDEC_REG_RESET);
264 writel(0x10, base + JPGDEC_REG_RESET);
265 }
266
mtk_jpeg_dec_reset(void __iomem * base)267 void mtk_jpeg_dec_reset(void __iomem *base)
268 {
269 mtk_jpeg_dec_soft_reset(base);
270 mtk_jpeg_dec_hard_reset(base);
271 }
272 EXPORT_SYMBOL_GPL(mtk_jpeg_dec_reset);
273
mtk_jpeg_dec_set_brz_factor(void __iomem * base,u8 yscale_w,u8 yscale_h,u8 uvscale_w,u8 uvscale_h)274 static void mtk_jpeg_dec_set_brz_factor(void __iomem *base, u8 yscale_w,
275 u8 yscale_h, u8 uvscale_w, u8 uvscale_h)
276 {
277 u32 val;
278
279 val = (uvscale_h << 12) | (uvscale_w << 8) |
280 (yscale_h << 4) | yscale_w;
281 writel(val, base + JPGDEC_REG_BRZ_FACTOR);
282 }
283
mtk_jpeg_dec_set_dst_bank0(void __iomem * base,u32 addr_y,u32 addr_u,u32 addr_v)284 static void mtk_jpeg_dec_set_dst_bank0(void __iomem *base, u32 addr_y,
285 u32 addr_u, u32 addr_v)
286 {
287 mtk_jpeg_verify_align(addr_y, 16, JPGDEC_REG_DEST_ADDR0_Y);
288 writel(addr_y, base + JPGDEC_REG_DEST_ADDR0_Y);
289 mtk_jpeg_verify_align(addr_u, 16, JPGDEC_REG_DEST_ADDR0_U);
290 writel(addr_u, base + JPGDEC_REG_DEST_ADDR0_U);
291 mtk_jpeg_verify_align(addr_v, 16, JPGDEC_REG_DEST_ADDR0_V);
292 writel(addr_v, base + JPGDEC_REG_DEST_ADDR0_V);
293 }
294
mtk_jpeg_dec_set_dst_bank1(void __iomem * base,u32 addr_y,u32 addr_u,u32 addr_v)295 static void mtk_jpeg_dec_set_dst_bank1(void __iomem *base, u32 addr_y,
296 u32 addr_u, u32 addr_v)
297 {
298 writel(addr_y, base + JPGDEC_REG_DEST_ADDR1_Y);
299 writel(addr_u, base + JPGDEC_REG_DEST_ADDR1_U);
300 writel(addr_v, base + JPGDEC_REG_DEST_ADDR1_V);
301 }
302
mtk_jpeg_dec_set_mem_stride(void __iomem * base,u32 stride_y,u32 stride_uv)303 static void mtk_jpeg_dec_set_mem_stride(void __iomem *base, u32 stride_y,
304 u32 stride_uv)
305 {
306 writel((stride_y & 0xFFFF), base + JPGDEC_REG_STRIDE_Y);
307 writel((stride_uv & 0xFFFF), base + JPGDEC_REG_STRIDE_UV);
308 }
309
mtk_jpeg_dec_set_img_stride(void __iomem * base,u32 stride_y,u32 stride_uv)310 static void mtk_jpeg_dec_set_img_stride(void __iomem *base, u32 stride_y,
311 u32 stride_uv)
312 {
313 writel((stride_y & 0xFFFF), base + JPGDEC_REG_IMG_STRIDE_Y);
314 writel((stride_uv & 0xFFFF), base + JPGDEC_REG_IMG_STRIDE_UV);
315 }
316
mtk_jpeg_dec_set_pause_mcu_idx(void __iomem * base,u32 idx)317 static void mtk_jpeg_dec_set_pause_mcu_idx(void __iomem *base, u32 idx)
318 {
319 writel(idx & 0x0003FFFFFF, base + JPGDEC_REG_PAUSE_MCU_NUM);
320 }
321
mtk_jpeg_dec_set_dec_mode(void __iomem * base,u32 mode)322 static void mtk_jpeg_dec_set_dec_mode(void __iomem *base, u32 mode)
323 {
324 writel(mode & 0x03, base + JPGDEC_REG_OPERATION_MODE);
325 }
326
mtk_jpeg_dec_set_bs_write_ptr(void __iomem * base,u32 ptr)327 static void mtk_jpeg_dec_set_bs_write_ptr(void __iomem *base, u32 ptr)
328 {
329 mtk_jpeg_verify_align(ptr, 16, JPGDEC_REG_FILE_BRP);
330 writel(ptr, base + JPGDEC_REG_FILE_BRP);
331 }
332
mtk_jpeg_dec_set_bs_info(void __iomem * base,u32 addr,u32 size,u32 bitstream_size)333 static void mtk_jpeg_dec_set_bs_info(void __iomem *base, u32 addr, u32 size,
334 u32 bitstream_size)
335 {
336 mtk_jpeg_verify_align(addr, 16, JPGDEC_REG_FILE_ADDR);
337 mtk_jpeg_verify_align(size, 128, JPGDEC_REG_FILE_TOTAL_SIZE);
338 writel(addr, base + JPGDEC_REG_FILE_ADDR);
339 writel(size, base + JPGDEC_REG_FILE_TOTAL_SIZE);
340 writel(bitstream_size, base + JPGDEC_REG_BIT_STREAM_SIZE);
341 }
342
mtk_jpeg_dec_set_comp_id(void __iomem * base,u32 id_y,u32 id_u,u32 id_v)343 static void mtk_jpeg_dec_set_comp_id(void __iomem *base, u32 id_y, u32 id_u,
344 u32 id_v)
345 {
346 u32 val;
347
348 val = ((id_y & 0x00FF) << 24) | ((id_u & 0x00FF) << 16) |
349 ((id_v & 0x00FF) << 8);
350 writel(val, base + JPGDEC_REG_COMP_ID);
351 }
352
mtk_jpeg_dec_set_total_mcu(void __iomem * base,u32 num)353 static void mtk_jpeg_dec_set_total_mcu(void __iomem *base, u32 num)
354 {
355 writel(num - 1, base + JPGDEC_REG_TOTAL_MCU_NUM);
356 }
357
mtk_jpeg_dec_set_comp0_du(void __iomem * base,u32 num)358 static void mtk_jpeg_dec_set_comp0_du(void __iomem *base, u32 num)
359 {
360 writel(num - 1, base + JPGDEC_REG_COMP0_DATA_UNIT_NUM);
361 }
362
mtk_jpeg_dec_set_du_membership(void __iomem * base,u32 member,u32 gmc,u32 isgray)363 static void mtk_jpeg_dec_set_du_membership(void __iomem *base, u32 member,
364 u32 gmc, u32 isgray)
365 {
366 if (isgray)
367 member = 0x3FFFFFFC;
368 member |= (isgray << 31) | (gmc << 30);
369 writel(member, base + JPGDEC_REG_DU_CTRL);
370 }
371
mtk_jpeg_dec_set_q_table(void __iomem * base,u32 id0,u32 id1,u32 id2)372 static void mtk_jpeg_dec_set_q_table(void __iomem *base, u32 id0, u32 id1,
373 u32 id2)
374 {
375 u32 val;
376
377 val = ((id0 & 0x0f) << 8) | ((id1 & 0x0f) << 4) | ((id2 & 0x0f) << 0);
378 writel(val, base + JPGDEC_REG_QT_ID);
379 }
380
mtk_jpeg_dec_set_dma_group(void __iomem * base,u32 mcu_group,u32 group_num,u32 last_mcu)381 static void mtk_jpeg_dec_set_dma_group(void __iomem *base, u32 mcu_group,
382 u32 group_num, u32 last_mcu)
383 {
384 u32 val;
385
386 val = (((mcu_group - 1) & 0x00FF) << 16) |
387 (((group_num - 1) & 0x007F) << 8) |
388 ((last_mcu - 1) & 0x00FF);
389 writel(val, base + JPGDEC_REG_WDMA_CTRL);
390 }
391
mtk_jpeg_dec_set_sampling_factor(void __iomem * base,u32 comp_num,u32 y_w,u32 y_h,u32 u_w,u32 u_h,u32 v_w,u32 v_h)392 static void mtk_jpeg_dec_set_sampling_factor(void __iomem *base, u32 comp_num,
393 u32 y_w, u32 y_h, u32 u_w,
394 u32 u_h, u32 v_w, u32 v_h)
395 {
396 u32 val;
397 u32 y_wh = (MTK_JPEG_DUNUM_MASK(y_w) << 2) | MTK_JPEG_DUNUM_MASK(y_h);
398 u32 u_wh = (MTK_JPEG_DUNUM_MASK(u_w) << 2) | MTK_JPEG_DUNUM_MASK(u_h);
399 u32 v_wh = (MTK_JPEG_DUNUM_MASK(v_w) << 2) | MTK_JPEG_DUNUM_MASK(v_h);
400
401 if (comp_num == 1)
402 val = 0;
403 else
404 val = (y_wh << 8) | (u_wh << 4) | v_wh;
405 writel(val, base + JPGDEC_REG_DU_NUM);
406 }
407
mtk_jpeg_dec_set_config(void __iomem * base,struct mtk_jpeg_dec_param * cfg,u32 bitstream_size,struct mtk_jpeg_bs * bs,struct mtk_jpeg_fb * fb)408 void mtk_jpeg_dec_set_config(void __iomem *base,
409 struct mtk_jpeg_dec_param *cfg,
410 u32 bitstream_size,
411 struct mtk_jpeg_bs *bs,
412 struct mtk_jpeg_fb *fb)
413 {
414 mtk_jpeg_dec_set_brz_factor(base, 0, 0, cfg->uv_brz_w, 0);
415 mtk_jpeg_dec_set_dec_mode(base, 0);
416 mtk_jpeg_dec_set_comp0_du(base, cfg->unit_num);
417 mtk_jpeg_dec_set_total_mcu(base, cfg->total_mcu);
418 mtk_jpeg_dec_set_bs_info(base, bs->str_addr, bs->size, bitstream_size);
419 mtk_jpeg_dec_set_bs_write_ptr(base, bs->end_addr);
420 mtk_jpeg_dec_set_du_membership(base, cfg->membership, 1,
421 (cfg->comp_num == 1) ? 1 : 0);
422 mtk_jpeg_dec_set_comp_id(base, cfg->comp_id[0], cfg->comp_id[1],
423 cfg->comp_id[2]);
424 mtk_jpeg_dec_set_q_table(base, cfg->qtbl_num[0],
425 cfg->qtbl_num[1], cfg->qtbl_num[2]);
426 mtk_jpeg_dec_set_sampling_factor(base, cfg->comp_num,
427 cfg->sampling_w[0],
428 cfg->sampling_h[0],
429 cfg->sampling_w[1],
430 cfg->sampling_h[1],
431 cfg->sampling_w[2],
432 cfg->sampling_h[2]);
433 mtk_jpeg_dec_set_mem_stride(base, cfg->mem_stride[0],
434 cfg->mem_stride[1]);
435 mtk_jpeg_dec_set_img_stride(base, cfg->img_stride[0],
436 cfg->img_stride[1]);
437 mtk_jpeg_dec_set_dst_bank0(base, fb->plane_addr[0],
438 fb->plane_addr[1], fb->plane_addr[2]);
439 mtk_jpeg_dec_set_dst_bank1(base, 0, 0, 0);
440 mtk_jpeg_dec_set_dma_group(base, cfg->dma_mcu, cfg->dma_group,
441 cfg->dma_last_mcu);
442 mtk_jpeg_dec_set_pause_mcu_idx(base, cfg->total_mcu);
443 }
444 EXPORT_SYMBOL_GPL(mtk_jpeg_dec_set_config);
445
mtk_jpegdec_put_buf(struct mtk_jpegdec_comp_dev * jpeg)446 static void mtk_jpegdec_put_buf(struct mtk_jpegdec_comp_dev *jpeg)
447 {
448 struct mtk_jpeg_src_buf *dst_done_buf, *tmp_dst_done_buf;
449 struct vb2_v4l2_buffer *dst_buffer;
450 struct list_head *temp_entry;
451 struct list_head *pos = NULL;
452 struct mtk_jpeg_ctx *ctx;
453 unsigned long flags;
454
455 ctx = jpeg->hw_param.curr_ctx;
456 if (unlikely(!ctx)) {
457 dev_err(jpeg->dev, "comp_jpeg ctx fail !!!\n");
458 return;
459 }
460
461 dst_buffer = jpeg->hw_param.dst_buffer;
462 if (!dst_buffer) {
463 dev_err(jpeg->dev, "comp_jpeg dst_buffer fail !!!\n");
464 return;
465 }
466
467 dst_done_buf = container_of(dst_buffer, struct mtk_jpeg_src_buf, b);
468
469 spin_lock_irqsave(&ctx->done_queue_lock, flags);
470 list_add_tail(&dst_done_buf->list, &ctx->dst_done_queue);
471 while (!list_empty(&ctx->dst_done_queue) &&
472 (pos != &ctx->dst_done_queue)) {
473 list_for_each_prev_safe(pos, temp_entry, &ctx->dst_done_queue) {
474 tmp_dst_done_buf = list_entry(pos,
475 struct mtk_jpeg_src_buf,
476 list);
477 if (tmp_dst_done_buf->frame_num ==
478 ctx->last_done_frame_num) {
479 list_del(&tmp_dst_done_buf->list);
480 v4l2_m2m_buf_done(&tmp_dst_done_buf->b,
481 VB2_BUF_STATE_DONE);
482 ctx->last_done_frame_num++;
483 }
484 }
485 }
486 spin_unlock_irqrestore(&ctx->done_queue_lock, flags);
487 }
488
mtk_jpegdec_timeout_work(struct work_struct * work)489 static void mtk_jpegdec_timeout_work(struct work_struct *work)
490 {
491 enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
492 struct mtk_jpegdec_comp_dev *cjpeg =
493 container_of(work, struct mtk_jpegdec_comp_dev,
494 job_timeout_work.work);
495 struct mtk_jpeg_dev *master_jpeg = cjpeg->master_dev;
496 struct vb2_v4l2_buffer *src_buf, *dst_buf;
497
498 src_buf = cjpeg->hw_param.src_buffer;
499 dst_buf = cjpeg->hw_param.dst_buffer;
500 v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
501
502 mtk_jpeg_dec_reset(cjpeg->reg_base);
503 clk_disable_unprepare(cjpeg->jdec_clk.clks->clk);
504 pm_runtime_put(cjpeg->dev);
505 cjpeg->hw_state = MTK_JPEG_HW_IDLE;
506 atomic_inc(&master_jpeg->dechw_rdy);
507 wake_up(&master_jpeg->dec_hw_wq);
508 v4l2_m2m_buf_done(src_buf, buf_state);
509 mtk_jpegdec_put_buf(cjpeg);
510 }
511
mtk_jpegdec_hw_irq_handler(int irq,void * priv)512 static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
513 {
514 struct vb2_v4l2_buffer *src_buf, *dst_buf;
515 struct mtk_jpeg_src_buf *jpeg_src_buf;
516 enum vb2_buffer_state buf_state;
517 struct mtk_jpeg_ctx *ctx;
518 u32 dec_irq_ret;
519 u32 irq_status;
520 int i;
521
522 struct mtk_jpegdec_comp_dev *jpeg = priv;
523 struct mtk_jpeg_dev *master_jpeg = jpeg->master_dev;
524
525 cancel_delayed_work(&jpeg->job_timeout_work);
526
527 ctx = jpeg->hw_param.curr_ctx;
528 src_buf = jpeg->hw_param.src_buffer;
529 dst_buf = jpeg->hw_param.dst_buffer;
530 v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true);
531
532 irq_status = mtk_jpeg_dec_get_int_status(jpeg->reg_base);
533 dec_irq_ret = mtk_jpeg_dec_enum_result(irq_status);
534 if (dec_irq_ret >= MTK_JPEG_DEC_RESULT_UNDERFLOW)
535 mtk_jpeg_dec_reset(jpeg->reg_base);
536
537 if (dec_irq_ret != MTK_JPEG_DEC_RESULT_EOF_DONE)
538 dev_warn(jpeg->dev, "Jpg Dec occurs unknown Err.");
539
540 jpeg_src_buf =
541 container_of(src_buf, struct mtk_jpeg_src_buf, b);
542
543 for (i = 0; i < dst_buf->vb2_buf.num_planes; i++)
544 vb2_set_plane_payload(&dst_buf->vb2_buf, i,
545 jpeg_src_buf->dec_param.comp_size[i]);
546
547 buf_state = VB2_BUF_STATE_DONE;
548 v4l2_m2m_buf_done(src_buf, buf_state);
549 mtk_jpegdec_put_buf(jpeg);
550 pm_runtime_put(ctx->jpeg->dev);
551 clk_disable_unprepare(jpeg->jdec_clk.clks->clk);
552
553 jpeg->hw_state = MTK_JPEG_HW_IDLE;
554 wake_up(&master_jpeg->dec_hw_wq);
555 atomic_inc(&master_jpeg->dechw_rdy);
556
557 return IRQ_HANDLED;
558 }
559
mtk_jpegdec_hw_init_irq(struct mtk_jpegdec_comp_dev * dev)560 static int mtk_jpegdec_hw_init_irq(struct mtk_jpegdec_comp_dev *dev)
561 {
562 struct platform_device *pdev = dev->plat_dev;
563 int ret;
564
565 dev->jpegdec_irq = platform_get_irq(pdev, 0);
566 if (dev->jpegdec_irq < 0)
567 return dev->jpegdec_irq;
568
569 ret = devm_request_irq(&pdev->dev,
570 dev->jpegdec_irq,
571 mtk_jpegdec_hw_irq_handler,
572 0,
573 pdev->name, dev);
574 if (ret) {
575 dev_err(&pdev->dev, "Failed to devm_request_irq %d (%d)",
576 dev->jpegdec_irq, ret);
577 return ret;
578 }
579
580 return 0;
581 }
582
mtk_jpegdec_destroy_workqueue(void * data)583 static void mtk_jpegdec_destroy_workqueue(void *data)
584 {
585 destroy_workqueue(data);
586 }
587
mtk_jpegdec_hw_probe(struct platform_device * pdev)588 static int mtk_jpegdec_hw_probe(struct platform_device *pdev)
589 {
590 struct mtk_jpegdec_clk *jpegdec_clk;
591 struct mtk_jpeg_dev *master_dev;
592 struct mtk_jpegdec_comp_dev *dev;
593 int ret, i;
594
595 struct device *decs = &pdev->dev;
596
597 if (!decs->parent)
598 return -EPROBE_DEFER;
599
600 master_dev = dev_get_drvdata(decs->parent);
601 if (!master_dev)
602 return -EPROBE_DEFER;
603
604 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
605 if (!dev)
606 return -ENOMEM;
607
608 dev->plat_dev = pdev;
609 dev->dev = &pdev->dev;
610
611 if (!master_dev->is_jpgdec_multihw) {
612 master_dev->is_jpgdec_multihw = true;
613 for (i = 0; i < MTK_JPEGDEC_HW_MAX; i++)
614 master_dev->dec_hw_dev[i] = NULL;
615
616 init_waitqueue_head(&master_dev->dec_hw_wq);
617 master_dev->workqueue = alloc_ordered_workqueue(MTK_JPEG_NAME,
618 WQ_MEM_RECLAIM
619 | WQ_FREEZABLE);
620 if (!master_dev->workqueue)
621 return -EINVAL;
622
623 ret = devm_add_action_or_reset(&pdev->dev, mtk_jpegdec_destroy_workqueue,
624 master_dev->workqueue);
625 if (ret)
626 return ret;
627 }
628
629 atomic_set(&master_dev->dechw_rdy, MTK_JPEGDEC_HW_MAX);
630 spin_lock_init(&dev->hw_lock);
631 dev->hw_state = MTK_JPEG_HW_IDLE;
632
633 INIT_DELAYED_WORK(&dev->job_timeout_work,
634 mtk_jpegdec_timeout_work);
635
636 jpegdec_clk = &dev->jdec_clk;
637
638 jpegdec_clk->clk_num = devm_clk_bulk_get_all(&pdev->dev,
639 &jpegdec_clk->clks);
640 if (jpegdec_clk->clk_num < 0)
641 return dev_err_probe(&pdev->dev,
642 jpegdec_clk->clk_num,
643 "Failed to get jpegdec clock count.\n");
644
645 dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
646 if (IS_ERR(dev->reg_base))
647 return PTR_ERR(dev->reg_base);
648
649 ret = mtk_jpegdec_hw_init_irq(dev);
650 if (ret)
651 return dev_err_probe(&pdev->dev, ret,
652 "Failed to register JPEGDEC irq handler.\n");
653
654 for (i = 0; i < MTK_JPEGDEC_HW_MAX; i++) {
655 if (master_dev->dec_hw_dev[i])
656 continue;
657
658 master_dev->dec_hw_dev[i] = dev;
659 master_dev->reg_decbase[i] = dev->reg_base;
660 dev->master_dev = master_dev;
661 }
662
663 platform_set_drvdata(pdev, dev);
664 pm_runtime_enable(&pdev->dev);
665
666 return 0;
667 }
668
669 static struct platform_driver mtk_jpegdec_hw_driver = {
670 .probe = mtk_jpegdec_hw_probe,
671 .driver = {
672 .name = "mtk-jpegdec-hw",
673 .of_match_table = of_match_ptr(mtk_jpegdec_hw_ids),
674 },
675 };
676
677 module_platform_driver(mtk_jpegdec_hw_driver);
678
679 MODULE_DESCRIPTION("MediaTek JPEG decode HW driver");
680 MODULE_LICENSE("GPL");
681