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Searched refs:nCur40MhzPrimeSC (Results 1 – 7 of 7) sorted by relevance

/linux-6.3-rc2/drivers/staging/rtl8723bs/hal/
A Drtl8723b_phycfg.c611 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) in phy_GetSecondaryChnl_8723B()
613 else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) in phy_GetSecondaryChnl_8723B()
653 PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1)); in phy_PostSetBwMode8723B()
655 PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC); in phy_PostSetBwMode8723B()
657 …PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_L… in phy_PostSetBwMode8723B()
714 u8 tmpnCur40MhzPrimeSC = pHalData->nCur40MhzPrimeSC; in PHY_HandleSwChnlAndSetBW8723B()
745 pHalData->nCur40MhzPrimeSC = ExtChnlOffsetOf40MHz; in PHY_HandleSwChnlAndSetBW8723B()
761 pHalData->nCur40MhzPrimeSC = tmpnCur40MhzPrimeSC; in PHY_HandleSwChnlAndSetBW8723B()
A Drtl8723b_dm.c94 ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC)); in Update_ODM_ComInfo_8723b()
A Drtl8723b_hal_init.c2487 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) { in SCMapping_8723B()
2489 } else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) { in SCMapping_8723B()
/linux-6.3-rc2/drivers/staging/rtl8192u/
A Dr819xU_phy.c1534 priv->nCur40MhzPrimeSC >> 1); in rtl8192_SetBWModeWorkItem()
1537 priv->nCur40MhzPrimeSC); in rtl8192_SetBWModeWorkItem()
1619 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; in rtl8192_SetBWMode()
1621 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; in rtl8192_SetBWMode()
1623 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; in rtl8192_SetBWMode()
A Dr8192U.h960 u8 nCur40MhzPrimeSC; member
A Dr8192U_core.c1287 tx_fwinfo->TxSubCarrier = priv->nCur40MhzPrimeSC; in rtl8192_tx()
/linux-6.3-rc2/drivers/staging/rtl8723bs/include/
A Dhal_data.h180 u8 nCur40MhzPrimeSC;/* Control channel sub-carrier */ member

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