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Searched refs:num_dcfclk_sta_targets (Results 1 – 5 of 5) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn302/
A Ddcn302_fpu.c206 unsigned int num_dcfclk_sta_targets = 4; in dcn302_fpu_update_bw_bounding_box() local
242 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn302_fpu_update_bw_bounding_box()
244 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box()
245 num_dcfclk_sta_targets++; in dcn302_fpu_update_bw_bounding_box()
246 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn302_fpu_update_bw_bounding_box()
248 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn302_fpu_update_bw_bounding_box()
255 num_dcfclk_sta_targets = i + 1; in dcn302_fpu_update_bw_bounding_box()
269 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn302_fpu_update_bw_bounding_box()
282 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
283 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn302_fpu_update_bw_bounding_box()
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/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn303/
A Ddcn303_fpu.c202 unsigned int num_dcfclk_sta_targets = 4; in dcn303_fpu_update_bw_bounding_box() local
238 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn303_fpu_update_bw_bounding_box()
239 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box()
240 num_dcfclk_sta_targets++; in dcn303_fpu_update_bw_bounding_box()
241 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn303_fpu_update_bw_bounding_box()
242 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn303_fpu_update_bw_bounding_box()
249 num_dcfclk_sta_targets = i + 1; in dcn303_fpu_update_bw_bounding_box()
263 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn303_fpu_update_bw_bounding_box()
276 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()
277 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn303_fpu_update_bw_bounding_box()
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/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn321/
A Ddcn321_fpu.c567 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; in dcn321_update_bw_bounding_box_fpu() local
589 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn321_update_bw_bounding_box_fpu()
591 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn321_update_bw_bounding_box_fpu()
592 num_dcfclk_sta_targets++; in dcn321_update_bw_bounding_box_fpu()
593 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn321_update_bw_bounding_box_fpu()
595 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn321_update_bw_bounding_box_fpu()
602 num_dcfclk_sta_targets = i + 1; in dcn321_update_bw_bounding_box_fpu()
617 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn321_update_bw_bounding_box_fpu()
630 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
631 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn321_update_bw_bounding_box_fpu()
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/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_resource.c2118 unsigned int num_dcfclk_sta_targets = 4; in dcn30_update_bw_bounding_box() local
2149 if (dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn30_update_bw_bounding_box()
2151 dcfclk_sta_targets[num_dcfclk_sta_targets] = dcn30_bb_max_clk.max_dcfclk_mhz; in dcn30_update_bw_bounding_box()
2152 num_dcfclk_sta_targets++; in dcn30_update_bw_bounding_box()
2153 } else if (dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn30_update_bw_bounding_box()
2155 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn30_update_bw_bounding_box()
2162 num_dcfclk_sta_targets = i + 1; in dcn30_update_bw_bounding_box()
2179 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn30_update_bw_bounding_box()
2192 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2193 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn30_update_bw_bounding_box()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c2576 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; in dcn32_update_bw_bounding_box_fpu() local
2603 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn32_update_bw_bounding_box_fpu()
2605 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn32_update_bw_bounding_box_fpu()
2606 num_dcfclk_sta_targets++; in dcn32_update_bw_bounding_box_fpu()
2607 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn32_update_bw_bounding_box_fpu()
2609 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn32_update_bw_bounding_box_fpu()
2616 num_dcfclk_sta_targets = i + 1; in dcn32_update_bw_bounding_box_fpu()
2631 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn32_update_bw_bounding_box_fpu()
2644 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn32_update_bw_bounding_box_fpu()
2645 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn32_update_bw_bounding_box_fpu()
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