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Searched refs:num_states (Results 1 – 25 of 48) sorted by relevance

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/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn302/
A Ddcn302_fpu.c126 .num_states = 1,
198 unsigned int num_states = 0; in dcn302_fpu_update_bw_bounding_box() local
284 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box()
288 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_fpu_update_bw_bounding_box()
296 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
297 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box()
298 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn302_fpu_update_bw_bounding_box()
301 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn302_fpu_update_bw_bounding_box()
303 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_fpu_update_bw_bounding_box()
307 dcn3_02_soc.num_states = num_states; in dcn302_fpu_update_bw_bounding_box()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn303/
A Ddcn303_fpu.c125 .num_states = 1,
194 unsigned int num_states = 0; in dcn303_fpu_update_bw_bounding_box() local
278 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box()
282 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_fpu_update_bw_bounding_box()
283 dram_speed_mts[num_states++] = in dcn303_fpu_update_bw_bounding_box()
292 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box()
296 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn303_fpu_update_bw_bounding_box()
298 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_fpu_update_bw_bounding_box()
302 dcn3_03_soc.num_states = num_states; in dcn303_fpu_update_bw_bounding_box()
303 for (i = 0; i < dcn3_03_soc.num_states; i++) { in dcn303_fpu_update_bw_bounding_box()
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/linux-6.3-rc2/arch/powerpc/kernel/
A Drtas-proc.c508 int num_states = 0; in ppc_rtas_process_sensor() local
518 if (state < num_states) { in ppc_rtas_process_sensor()
526 if (state < num_states) { in ppc_rtas_process_sensor()
539 if (state < num_states) { in ppc_rtas_process_sensor()
547 if (state < num_states) { in ppc_rtas_process_sensor()
559 if (state < num_states) in ppc_rtas_process_sensor()
572 if (state < num_states) { in ppc_rtas_process_sensor()
579 num_states = sizeof(battery_cyclestate) / in ppc_rtas_process_sensor()
581 if (state < num_states) { in ppc_rtas_process_sensor()
590 if (state < num_states) { in ppc_rtas_process_sensor()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn321/
A Ddcn321_fpu.c122 .num_states = 1,
559 unsigned int i = 0, j = 0, num_states = 0; in dcn321_update_bw_bounding_box_fpu() local
632 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn321_update_bw_bounding_box_fpu()
636 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn321_update_bw_bounding_box_fpu()
644 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
645 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn321_update_bw_bounding_box_fpu()
646 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn321_update_bw_bounding_box_fpu()
649 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn321_update_bw_bounding_box_fpu()
651 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn321_update_bw_bounding_box_fpu()
655 dcn3_21_soc.num_states = num_states; in dcn321_update_bw_bounding_box_fpu()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c212 .num_states = 5,
301 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
344 for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) { in dcn301_update_bw_bounding_box()
369 dcn3_01_soc.num_states = clk_table->num_entries; in dcn301_update_bw_bounding_box()
371 s[dcn3_01_soc.num_states] = in dcn301_update_bw_bounding_box()
372 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1]; in dcn301_update_bw_bounding_box()
373 s[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states; in dcn301_update_bw_bounding_box()
/linux-6.3-rc2/drivers/regulator/
A Dirq_helpers.c62 num_rdevs = rid->num_states; in regulator_notifier_isr_work()
167 num_rdevs = rid->num_states; in regulator_notifier_isr()
291 h->rdata.num_states = rdev_amount; in init_rdev_state()
308 for (i = 0; i < h->rdata.num_states; i++) in init_rdev_errors()
427 if (WARN_ON(rid->num_states != 1 || hweight32(err) != 1)) in regulator_irq_map_event_simple()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c124 .num_states = 1,
1120 if (*vlevel < context->bw_ctx.dml.soc.num_states) { in dcn32_full_validate_bw_helper()
1134 (*vlevel == context->bw_ctx.dml.soc.num_states || in dcn32_full_validate_bw_helper()
1604 int vlevel = context->bw_ctx.dml.soc.num_states; in dcn32_internal_validate_bw()
1633 (vlevel == context->bw_ctx.dml.soc.num_states || in dcn32_internal_validate_bw()
1664 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn32_internal_validate_bw()
2003 if (dcn3_2_soc.num_states > 2) { in dcn32_calculate_wm_and_dlg_fpu()
2037 if (dcn3_2_soc.num_states > 2) { in dcn32_calculate_wm_and_dlg_fpu()
2566 unsigned int i = 0, j = 0, num_states = 0; in dcn32_update_bw_bounding_box_fpu() local
2669 dcn3_2_soc.num_states = num_states; in dcn32_update_bw_bounding_box_fpu()
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A Ddisplay_mode_vba_32.c113 mode_lib->vba.MaxDppclk[v->soc.num_states - 1])); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1651 start_state = v->soc.num_states - 1; in mode_support_configuration()
1702 || i == v->soc.num_states - 1) in mode_support_configuration()
1707 || i == v->soc.num_states - 1 in mode_support_configuration()
1738 start_state = v->soc.num_states - 1; in dml32_ModeSupportAndSystemConfigurationFull()
2030 for (i = start_state; i < v->soc.num_states; i++) { in dml32_ModeSupportAndSystemConfigurationFull()
2307 for (i = start_state; i < v->soc.num_states; ++i) { in dml32_ModeSupportAndSystemConfigurationFull()
2406 for (i = start_state; i < v->soc.num_states; ++i) { in dml32_ModeSupportAndSystemConfigurationFull()
2423 for (i = start_state; i < v->soc.num_states; ++i) { in dml32_ModeSupportAndSystemConfigurationFull()
2441 for (i = start_state; i < v->soc.num_states; i++) { in dml32_ModeSupportAndSystemConfigurationFull()
[all …]
/linux-6.3-rc2/net/netfilter/ipvs/
A Dip_vs_proto_ah_esp.c119 .num_states = 1,
141 .num_states = 1,
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_resource.c1689 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1693 (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states || in dcn30_internal_validate_bw()
1706 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1715 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
2110 unsigned int num_states = 0; in dcn30_update_bw_bounding_box() local
2194 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2198 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()
2207 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2211 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn30_update_bw_bounding_box()
2213 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddcn314_fpu.c149 .num_states = 5,
217 for (closest_clk_lvl = 0, j = dcn3_14_soc.num_states - 1; j >= 0; j--) { in dcn314_update_bw_bounding_box_fpu()
225 closest_clk_lvl = dcn3_14_soc.num_states - 1; in dcn314_update_bw_bounding_box_fpu()
259 dcn3_14_soc.num_states = clk_table->num_entries; in dcn314_update_bw_bounding_box_fpu()
A Ddisplay_mode_vba_314.c4164 for (i = 0; i < v->soc.num_states; i++) {
4348 for (i = 0; i < v->soc.num_states; i++) {
4386 for (i = 0; i < v->soc.num_states; i++) {
4530 for (i = 0; i < v->soc.num_states; i++) {
4559 for (i = 0; i < v->soc.num_states; ++i) {
4572 for (i = 0; i < v->soc.num_states; i++) {
4592 for (i = 0; i < v->soc.num_states; i++) {
4643 for (i = 0; i < v->soc.num_states; ++i) {
4730 for (i = 0; i < v->soc.num_states; i++) {
4962 for (i = 0; i < v->soc.num_states; ++i) {
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddcn31_fpu.c169 .num_states = 5,
412 .num_states = 5,
599 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) { in dcn31_update_bw_bounding_box()
631 dcn3_1_soc.num_states = clk_table->num_entries; in dcn31_update_bw_bounding_box()
696 dcn3_15_soc.num_states = clk_table->num_entries; in dcn315_update_bw_bounding_box()
747 for (closest_clk_lvl = 0, j = dcn3_16_soc.num_states - 1; j >= 0; j--) { in dcn316_update_bw_bounding_box()
757 closest_clk_lvl = dcn3_16_soc.num_states - 1; in dcn316_update_bw_bounding_box()
792 dcn3_16_soc.num_states = clk_table->num_entries; in dcn316_update_bw_bounding_box()
A Ddisplay_mode_vba_31.c4067 for (i = 0; i < v->soc.num_states; i++) {
4250 for (i = 0; i < v->soc.num_states; i++) {
4288 for (i = 0; i < v->soc.num_states; i++) {
4432 for (i = 0; i < v->soc.num_states; i++) {
4460 for (i = 0; i < v->soc.num_states; ++i) {
4473 for (i = 0; i < v->soc.num_states; i++) {
4493 for (i = 0; i < v->soc.num_states; i++) {
4544 for (i = 0; i < v->soc.num_states; ++i) {
4633 for (i = 0; i < v->soc.num_states; i++) {
4863 for (i = 0; i < v->soc.num_states; ++i) {
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddcn20_fpu.c289 .num_states = 5,
400 .num_states = 5,
654 .num_states = 8
1744 if (num_states == 0) in dcn20_update_bounding_box()
1760 for (i = 0; i < num_states; i++) { in dcn20_update_bounding_box()
1791 bb->num_states = num_calculated_states; in dcn20_update_bounding_box()
1807 for (i = 0; i < bb->num_states; i++) { in dcn20_cap_soc_clocks()
1863 bb->num_states--; in dcn20_cap_soc_clocks()
2092 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
2338 …dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1… in dcn21_update_bw_bounding_box()
[all …]
A Ddcn20_fpu.h61 unsigned int num_states);
A Ddisplay_mode_vba_20.c2598 for (k = 0; k <= mode_lib->vba.soc.num_states; k++) in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3441 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3523 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3874 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3889 && i == mode_lib->vba.soc.num_states) in dml20_ModeSupportAndSystemConfigurationFull()
3896 && i == mode_lib->vba.soc.num_states) in dml20_ModeSupportAndSystemConfigurationFull()
3970 if (i != mode_lib->vba.soc.num_states) { in dml20_ModeSupportAndSystemConfigurationFull()
4002 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
4383 for (i = 0; i <= locals->soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
4395 for (i = 0; i <= locals->soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
[all …]
A Ddisplay_mode_vba_20v2.c2671 for (k = 0; k <= mode_lib->vba.soc.num_states; k++) in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3548 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3630 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3981 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4000 && i == mode_lib->vba.soc.num_states) in dml20v2_ModeSupportAndSystemConfigurationFull()
4007 && i == mode_lib->vba.soc.num_states) in dml20v2_ModeSupportAndSystemConfigurationFull()
4084 if (i != mode_lib->vba.soc.num_states) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4116 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4504 for (i = 0; i <= locals->soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4516 for (i = 0; i <= locals->soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_socbb.h78 uint32_t num_states; member
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/
A Ddm_pp_smu.h229 unsigned int *clock_values_in_khz, unsigned int *num_states);
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_resource.c1917 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1922 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
2071 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2144 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
2365 unsigned int num_states = 0; in init_soc_bounding_box() local
2372 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); in init_soc_bounding_box()
2387 if (clock_limits_available && uclk_states_available && num_states) { in init_soc_bounding_box()
2389 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states); in init_soc_bounding_box()
2593 if (loaded_bb->num_states == 1) { in dcn20_resource_construct()
2601 } else if (loaded_bb->num_states > 1) { in dcn20_resource_construct()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddisplay_mode_vba_30.c3858 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
4014 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
4053 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
4181 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
4192 for (i = 0; i < v->soc.num_states; ++i) { in dml30_ModeSupportAndSystemConfigurationFull()
4204 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
4224 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
4340 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
5082 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
5143 for (i = v->soc.num_states - 1; i >= 0; i--) { in dml30_ModeSupportAndSystemConfigurationFull()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn21/
A Ddisplay_mode_vba_21.c3674 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
3716 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
4070 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
4094 && i == mode_lib->vba.soc.num_states) in dml21_ModeSupportAndSystemConfigurationFull()
4101 && i == mode_lib->vba.soc.num_states) in dml21_ModeSupportAndSystemConfigurationFull()
4178 if (i != mode_lib->vba.soc.num_states) { in dml21_ModeSupportAndSystemConfigurationFull()
4210 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
4227 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
4259 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
4384 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_pp_smu.c708 unsigned int *clock_values_in_khz, unsigned int *num_states) in pp_nv_get_uclk_dpm_states() argument
716 num_states); in pp_nv_get_uclk_dpm_states()
/linux-6.3-rc2/include/linux/regulator/
A Ddriver.h496 int num_states; member

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