num_valid_sets (reference) in projects: linux-6.3-rc2

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Searched refs:num_valid_sets (Results 1 – 6 of 6) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
A D	dcn316_clk_mgr.c	357 int i, num_valid_sets; in dcn316_build_watermark_ranges() local 359 num_valid_sets = 0; in dcn316_build_watermark_ranges() 369 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn316_build_watermark_ranges() 370 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn316_build_watermark_ranges() 374 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn316_build_watermark_ranges() 377 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn316_build_watermark_ranges() 380 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn316_build_watermark_ranges() 385 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn316_build_watermark_ranges() 386 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn316_build_watermark_ranges() 391 num_valid_sets++; in dcn316_build_watermark_ranges() [all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A D	vg_clk_mgr.c	390 int i, num_valid_sets; in vg_build_watermark_ranges() local 392 num_valid_sets = 0; in vg_build_watermark_ranges() 402 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in vg_build_watermark_ranges() 403 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in vg_build_watermark_ranges() 407 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in vg_build_watermark_ranges() 410 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in vg_build_watermark_ranges() 413 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in vg_build_watermark_ranges() 418 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in vg_build_watermark_ranges() 419 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in vg_build_watermark_ranges() 424 num_valid_sets++; in vg_build_watermark_ranges() [all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
A D	dcn315_clk_mgr.c	379 int i, num_valid_sets; in dcn315_build_watermark_ranges() local 381 num_valid_sets = 0; in dcn315_build_watermark_ranges() 391 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn315_build_watermark_ranges() 392 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn315_build_watermark_ranges() 396 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn315_build_watermark_ranges() 399 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn315_build_watermark_ranges() 402 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn315_build_watermark_ranges() 407 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn315_build_watermark_ranges() 408 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn315_build_watermark_ranges() 413 num_valid_sets++; in dcn315_build_watermark_ranges() [all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
A D	dcn31_clk_mgr.c	422 int i, num_valid_sets; in dcn31_build_watermark_ranges() local 424 num_valid_sets = 0; in dcn31_build_watermark_ranges() 434 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges() 435 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges() 439 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn31_build_watermark_ranges() 442 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn31_build_watermark_ranges() 445 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn31_build_watermark_ranges() 450 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges() 451 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges() 456 num_valid_sets++; in dcn31_build_watermark_ranges() [all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
A D	rn_clk_mgr.c	456 int i, num_valid_sets; in build_watermark_ranges() local 458 num_valid_sets = 0; in build_watermark_ranges() 465 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; in build_watermark_ranges() 466 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type; in build_watermark_ranges() 468 …ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MI… in build_watermark_ranges() 469 …ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MA… in build_watermark_ranges() 472 if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) { in build_watermark_ranges() 474 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = 0; in build_watermark_ranges() 489 num_valid_sets++; in build_watermark_ranges() 492 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */ in build_watermark_ranges() [all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
A D	dcn314_clk_mgr.c	440 int i, num_valid_sets; in dcn314_build_watermark_ranges() local 442 num_valid_sets = 0; in dcn314_build_watermark_ranges() 452 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn314_build_watermark_ranges() 453 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn314_build_watermark_ranges() 457 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn314_build_watermark_ranges() 460 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn314_build_watermark_ranges() 463 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn314_build_watermark_ranges() 468 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn314_build_watermark_ranges() 469 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn314_build_watermark_ranges() 474 num_valid_sets++; in dcn314_build_watermark_ranges() [all …]

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