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Searched refs:pdiv (Results 1 – 25 of 39) sorted by relevance

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/linux-6.3-rc2/drivers/clk/tegra/
A Dclk-tegra124.c153 { .pdiv = 1, .hw_val = 0 },
154 { .pdiv = 2, .hw_val = 1 },
155 { .pdiv = 3, .hw_val = 2 },
156 { .pdiv = 4, .hw_val = 3 },
157 { .pdiv = 5, .hw_val = 4 },
158 { .pdiv = 6, .hw_val = 5 },
249 { .pdiv = 1, .hw_val = 0 },
250 { .pdiv = 2, .hw_val = 1 },
251 { .pdiv = 3, .hw_val = 2 },
252 { .pdiv = 4, .hw_val = 3 },
[all …]
A Dclk-tegra114.c211 { .pdiv = 1, .hw_val = 0 },
212 { .pdiv = 2, .hw_val = 1 },
213 { .pdiv = 4, .hw_val = 3 },
214 { .pdiv = 8, .hw_val = 5 },
215 { .pdiv = 16, .hw_val = 7 },
216 { .pdiv = 0, .hw_val = 0 },
285 { .pdiv = 1, .hw_val = 0 },
286 { .pdiv = 2, .hw_val = 1 },
287 { .pdiv = 0, .hw_val = 0 },
442 { .pdiv = 1, .hw_val = 1 },
[all …]
A Dclk-tegra210.c1486 u32 pdiv; in tegra210_pll_fixed_mdiv_cfg() local
1580 { .pdiv = 1, .hw_val = 0 },
1581 { .pdiv = 2, .hw_val = 1 },
1582 { .pdiv = 3, .hw_val = 2 },
1583 { .pdiv = 4, .hw_val = 3 },
1584 { .pdiv = 5, .hw_val = 4 },
1585 { .pdiv = 6, .hw_val = 5 },
1606 if (pdiv) in pll_qlin_p_to_pdiv()
1607 *pdiv = i; in pll_qlin_p_to_pdiv()
1637 if (pdiv) in pll_expo_p_to_pdiv()
[all …]
A Dclk-pll.c486 while (p_tohw->pdiv) { in _p_div_to_hw()
507 while (p_tohw->pdiv) { in _hw_to_p_div()
509 return p_tohw->pdiv; in _hw_to_p_div()
870 int pdiv; in clk_pll_recalc_rate() local
893 pdiv = 1; in clk_pll_recalc_rate()
896 if (pdiv < 0) { in clk_pll_recalc_rate()
899 pdiv = 1; in clk_pll_recalc_rate()
906 cfg.m *= pdiv; in clk_pll_recalc_rate()
2240 while (p_tohw->pdiv) { in tegra_clk_register_pllc()
2241 if (p_tohw->pdiv == 2) { in tegra_clk_register_pllc()
[all …]
A Dclk-tegra20.c268 { .pdiv = 1, .hw_val = 1 },
269 { .pdiv = 0, .hw_val = 0 },
361 { .pdiv = 1, .hw_val = 1 },
362 { .pdiv = 2, .hw_val = 0 },
363 { .pdiv = 0, .hw_val = 0 },
A Dclk-tegra30.c273 { .pdiv = 1, .hw_val = 1 },
274 { .pdiv = 2, .hw_val = 0 },
275 { .pdiv = 0, .hw_val = 0 },
340 { .pdiv = 18, .hw_val = 18 },
341 { .pdiv = 24, .hw_val = 24 },
342 { .pdiv = 0, .hw_val = 0 },
/linux-6.3-rc2/drivers/clk/samsung/
A Dclk-pll.c153 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll2126_recalc_rate() local
186 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll3000_recalc_rate() local
195 do_div(fvco, pdiv << sdiv); in samsung_pll3000_recalc_rate()
223 u32 mdiv, pdiv, sdiv, pll_con; in samsung_pll35xx_recalc_rate() local
232 do_div(fvco, (pdiv << sdiv)); in samsung_pll35xx_recalc_rate()
339 do_div(fvco, (pdiv << sdiv)); in samsung_pll36xx_recalc_rate()
446 do_div(fvco, (pdiv << sdiv)); in samsung_pll0822x_recalc_rate()
534 do_div(fvco, (pdiv << sdiv)); in samsung_pll0831x_recalc_rate()
632 do_div(fvco, (pdiv << sdiv)); in samsung_pll45xx_recalc_rate()
768 do_div(fvco, (pdiv << sdiv)); in samsung_pll46xx_recalc_rate()
[all …]
A Dclk-pll.h52 .pdiv = (_p), \
61 .pdiv = (_p), \
71 .pdiv = (_p), \
81 .pdiv = (_p), \
92 .pdiv = (_p), \
104 unsigned int pdiv; member
/linux-6.3-rc2/drivers/clk/imx/
A Dclk-pll14xx.c113 pdiv *= 65536; in pll14xx_calc_rate()
115 do_div(fvco, pdiv << sdiv); in pll14xx_calc_rate()
135 int mdiv, pdiv, sdiv, kdiv; in imx_pll14xx_calc_settings() local
158 t->pdiv = tt->pdiv; in imx_pll14xx_calc_settings()
166 pdiv = FIELD_GET(PDIV_MASK, pll_div_ctl0); in imx_pll14xx_calc_settings()
182 t->pdiv = pdiv; in imx_pll14xx_calc_settings()
189 for (pdiv = 1; pdiv <= 7; pdiv++) { in imx_pll14xx_calc_settings()
204 t->pdiv = pdiv; in imx_pll14xx_calc_settings()
250 u32 mdiv, pdiv, sdiv, kdiv, pll_div_ctl0, pll_div_ctl1; in clk_pll14xx_recalc_rate() local
254 pdiv = FIELD_GET(PDIV_MASK, pll_div_ctl0); in clk_pll14xx_recalc_rate()
[all …]
/linux-6.3-rc2/drivers/clk/
A Dclk-cdce925.c68 u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */ member
295 0x03, (pdiv >> 8) & 0x03); in cdce925_clk_set_pdiv()
296 regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF); in cdce925_clk_set_pdiv()
299 regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv); in cdce925_clk_set_pdiv()
355 cdce925_clk_set_pdiv(data, data->pdiv); in cdce925_clk_prepare()
373 if (data->pdiv) in cdce925_clk_recalc_rate()
374 return parent_rate / data->pdiv; in cdce925_clk_recalc_rate()
460 data->pdiv = cdce925_calc_divider(rate, parent_rate); in cdce925_clk_set_rate()
507 data->pdiv = cdce925_y1_calc_divider(rate, parent_rate); in cdce925_clk_y1_set_rate()
748 data->clk[0].pdiv = 1; in cdce925_probe()
[all …]
/linux-6.3-rc2/drivers/clk/bcm/
A Dclk-iproc-pll.c104 vco_out->pdiv = 1; in pll_calc_param()
282 unsigned int pdiv; in pll_fractional_change_only() local
297 pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); in pll_fractional_change_only()
299 if (pdiv != vco->pdiv) in pll_fractional_change_only()
321 if (vco->pdiv == 0) in pll_set_rate()
412 val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift); in pll_set_rate()
413 val |= vco->pdiv << ctrl->pdiv.shift; in pll_set_rate()
455 unsigned int pdiv; in iproc_pll_recalc_rate() local
484 pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); in iproc_pll_recalc_rate()
488 if (pdiv == 0) in iproc_pll_recalc_rate()
[all …]
A Dclk-iproc-armpll.c192 unsigned int pdiv; in iproc_arm_pll_recalc_rate() local
208 pdiv = (val >> IPROC_CLK_PLLARMA_PDIV_SHIFT) & in iproc_arm_pll_recalc_rate()
210 if (pdiv == 0) in iproc_arm_pll_recalc_rate()
211 pdiv = 16; in iproc_arm_pll_recalc_rate()
220 pll->rate = (pll->rate / pdiv) / mdiv; in iproc_arm_pll_recalc_rate()
225 (unsigned int)(ndiv >> 20), pdiv, mdiv); in iproc_arm_pll_recalc_rate()
A Dclk-sr.c43 .pdiv = REG_VAL(0x14, 0, 4),
103 .pdiv = REG_VAL(0x14, 0, 4),
162 .pdiv = REG_VAL(0x14, 0, 4),
197 .pdiv = REG_VAL(0x14, 0, 4),
251 .pdiv = REG_VAL(0x14, 0, 4),
287 .pdiv = REG_VAL(0x4, 26, 4),
332 .pdiv = REG_VAL(0x4, 26, 4),
371 .pdiv = REG_VAL(0x4, 26, 4),
A Dclk-ns2.c37 .pdiv = REG_VAL(0x8, 0, 4),
100 .pdiv = REG_VAL(0x8, 0, 4),
162 .pdiv = REG_VAL(0x8, 0, 4),
224 .pdiv = REG_VAL(0x8, 0, 4),
A Dclk-cygnus.c56 .pdiv = REG_VAL(0x14, 0, 4),
114 .pdiv = REG_VAL(0x4, 26, 4),
192 .pdiv = REG_VAL(0x14, 0, 4),
271 .pdiv = REG_VAL(0x44, 0, 4),
A Dclk-iproc.h88 unsigned int pdiv; member
164 struct iproc_clk_reg_op pdiv; member
A Dclk-nsp.c42 .pdiv = REG_VAL(0x18, 24, 3),
99 .pdiv = REG_VAL(0x4, 28, 3),
/linux-6.3-rc2/drivers/thermal/tegra/
A Dtegra124-soctherm.c51 .pdiv = 8,
70 .pdiv = 8,
89 .pdiv = 8,
106 .pdiv = 8,
A Dtegra132-soctherm.c51 .pdiv = 8,
70 .pdiv = 8,
89 .pdiv = 8,
106 .pdiv = 8,
A Dtegra210-soctherm.c52 .pdiv = 8,
71 .pdiv = 8,
90 .pdiv = 8,
107 .pdiv = 8,
A Dsoctherm.h77 u32 pdiv, pdiv_ate, pdiv_mask; member
89 u32 tall, tiddq_en, ten_count, pdiv, pdiv_ate, tsample, tsample_ate; member
/linux-6.3-rc2/drivers/gpu/drm/i915/display/
A Dintel_dpll_mgr.c1463 u32 pdiv; member
1488 params->pdiv = 0; in skl_wrpll_params_populate()
1491 params->pdiv = 1; in skl_wrpll_params_populate()
1494 params->pdiv = 2; in skl_wrpll_params_populate()
1497 params->pdiv = 4; in skl_wrpll_params_populate()
2378 *pdiv = 2; in icl_wrpll_get_multipliers()
2382 *pdiv = 2; in icl_wrpll_get_multipliers()
2386 *pdiv = 3; in icl_wrpll_get_multipliers()
2390 *pdiv = 5; in icl_wrpll_get_multipliers()
2394 *pdiv = 7; in icl_wrpll_get_multipliers()
[all …]
/linux-6.3-rc2/drivers/clk/st/
A Dclk-flexgen.c39 struct clk_divider pdiv; member
142 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; in flexgen_recalc_rate()
158 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; in flexgen_set_rate()
243 fgxbar->pdiv.lock = lock; in clk_register_flexgen()
244 fgxbar->pdiv.reg = reg + 0x58 + idx * 4; in clk_register_flexgen()
245 fgxbar->pdiv.width = 10; in clk_register_flexgen()
/linux-6.3-rc2/drivers/cpufreq/
A Dbrcmstb-avs-cpufreq.c341 static void brcm_avs_parse_p1(u32 p1, unsigned int *mdiv_p0, unsigned int *pdiv, in brcm_avs_parse_p1() argument
345 *pdiv = (p1 >> PDIV_SHIFT) & PDIV_MASK; in brcm_avs_parse_p1()
679 unsigned int ndiv, pdiv; in show_brcm_avs_pmap() local
685 brcm_avs_parse_p1(pmap.p1, &mdiv_p0, &pdiv, &ndiv); in show_brcm_avs_pmap()
689 pmap.p1, pmap.p2, ndiv, pdiv, mdiv_p0, mdiv_p1, mdiv_p2, in show_brcm_avs_pmap()
/linux-6.3-rc2/arch/arm/mach-ep93xx/
A Dclock.c278 int pdiv = 0, div = 0; in ep93xx_ddiv_set_rate() local
292 pdiv = __pdiv - 3; in ep93xx_ddiv_set_rate()
307 val |= (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div; in ep93xx_ddiv_set_rate()

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