Home
last modified time | relevance | path

Searched refs:pfit_control (Results 1 – 8 of 8) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/i915/display/
A Dintel_panel.c469 u32 *pfit_control) in i965_scale_aspect() argument
480 *pfit_control |= PFIT_ENABLE | in i965_scale_aspect()
483 *pfit_control |= PFIT_ENABLE | in i965_scale_aspect()
516 *pfit_control |= (PFIT_ENABLE | in i9xx_scale_aspect()
531 *pfit_control |= (PFIT_ENABLE | in i9xx_scale_aspect()
537 *pfit_control |= (PFIT_ENABLE | in i9xx_scale_aspect()
584 pfit_control |= PFIT_ENABLE; in gmch_panel_fitting()
586 pfit_control |= PFIT_SCALING_AUTO; in gmch_panel_fitting()
588 pfit_control |= (VERT_AUTO_SCALE | in gmch_panel_fitting()
605 if ((pfit_control & PFIT_ENABLE) == 0) { in gmch_panel_fitting()
[all …]
A Dintel_overlay.c938 u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL); in update_pfit_vscale_ratio() local
948 if (pfit_control & VERT_AUTO_SCALE) in update_pfit_vscale_ratio()
/linux-6.3-rc2/drivers/gpu/drm/gma500/
A Dcdv_intel_lvds.c267 u32 pfit_control; in cdv_intel_lvds_mode_set() local
282 pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE | in cdv_intel_lvds_mode_set()
286 pfit_control = 0; in cdv_intel_lvds_mode_set()
288 pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT; in cdv_intel_lvds_mode_set()
291 pfit_control |= PANEL_8TO6_DITHER_ENABLE; in cdv_intel_lvds_mode_set()
293 REG_WRITE(PFIT_CONTROL, pfit_control); in cdv_intel_lvds_mode_set()
A Dpsb_intel_lvds.c461 u32 pfit_control; in psb_intel_lvds_mode_set() local
476 pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE | in psb_intel_lvds_mode_set()
480 pfit_control = 0; in psb_intel_lvds_mode_set()
483 pfit_control |= PANEL_8TO6_DITHER_ENABLE; in psb_intel_lvds_mode_set()
485 REG_WRITE(PFIT_CONTROL, pfit_control); in psb_intel_lvds_mode_set()
A Doaktrail_crtc.c349 u32 pfit_control; in oaktrail_panel_fitter_pipe() local
351 pfit_control = REG_READ(PFIT_CONTROL); in oaktrail_panel_fitter_pipe()
354 if ((pfit_control & PFIT_ENABLE) == 0) in oaktrail_panel_fitter_pipe()
356 return (pfit_control >> 29) & 3; in oaktrail_panel_fitter_pipe()
A Dpsb_intel_display.c82 u32 pfit_control; in psb_intel_panel_fitter_pipe() local
84 pfit_control = REG_READ(PFIT_CONTROL); in psb_intel_panel_fitter_pipe()
87 if ((pfit_control & PFIT_ENABLE) == 0) in psb_intel_panel_fitter_pipe()
A Dcdv_intel_display.c561 u32 pfit_control; in cdv_intel_panel_fitter_pipe() local
563 pfit_control = REG_READ(PFIT_CONTROL); in cdv_intel_panel_fitter_pipe()
566 if ((pfit_control & PFIT_ENABLE) == 0) in cdv_intel_panel_fitter_pipe()
568 return (pfit_control >> 29) & 0x3; in cdv_intel_panel_fitter_pipe()
A Dcdv_intel_dp.c1089 uint32_t pfit_control; in cdv_intel_dp_mode_set() local
1094 pfit_control = PFIT_ENABLE; in cdv_intel_dp_mode_set()
1096 pfit_control = 0; in cdv_intel_dp_mode_set()
1098 pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT; in cdv_intel_dp_mode_set()
1100 REG_WRITE(PFIT_CONTROL, pfit_control); in cdv_intel_dp_mode_set()

Completed in 19 milliseconds