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Searched refs:phase (Results 1 – 25 of 447) sorted by relevance

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/linux-6.3-rc2/drivers/clk/hisilicon/
A Dclk-hisi-phase.c47 regval = readl(phase->reg); in hisi_clk_get_phase()
48 regval = (regval & phase->mask) >> phase->shift; in hisi_clk_get_phase()
78 val = readl(phase->reg); in hisi_clk_set_phase()
79 val &= ~phase->mask; in hisi_clk_set_phase()
80 val |= regval << phase->shift; in hisi_clk_set_phase()
81 writel(val, phase->reg); in hisi_clk_set_phase()
97 struct clk_hisi_phase *phase; in clk_register_hisi_phase() local
101 if (!phase) in clk_register_hisi_phase()
111 phase->shift = clks->shift; in clk_register_hisi_phase()
113 phase->lock = lock; in clk_register_hisi_phase()
[all …]
/linux-6.3-rc2/drivers/clk/sunxi-ng/
A Dccu_phase.c15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
58 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_set_phase() local
110 spin_lock_irqsave(phase->common.lock, flags); in ccu_phase_set_phase()
111 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_set_phase()
112 reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift); in ccu_phase_set_phase()
113 writel(reg | (delay << phase->shift), in ccu_phase_set_phase()
114 phase->common.base + phase->common.reg); in ccu_phase_set_phase()
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/linux-6.3-rc2/drivers/gpu/drm/tidss/
A Dtidss_dispc_regs.h120 #define DISPC_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4) argument
122 #define DISPC_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4) argument
125 #define DISPC_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4) argument
127 #define DISPC_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4) argument
130 #define DISPC_VID_FIR_COEF_V0(phase) (0x134 + (phase) * 4) argument
132 #define DISPC_VID_FIR_COEF_V0_C(phase) (0x158 + (phase) * 4) argument
135 #define DISPC_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4) argument
137 #define DISPC_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4) argument
/linux-6.3-rc2/drivers/clk/sunxi/
A Dclk-mod0.c179 value = readl(phase->reg); in mmc_get_phase()
268 value &= ~GENMASK(phase->offset + 3, phase->offset); in mmc_set_phase()
324 struct mmc_phase *phase; in sunxi_mmc_setup() local
326 phase = kmalloc(sizeof(*phase), GFP_KERNEL); in sunxi_mmc_setup()
327 if (!phase) in sunxi_mmc_setup()
330 phase->hw.init = &init; in sunxi_mmc_setup()
331 phase->reg = reg; in sunxi_mmc_setup()
332 phase->lock = lock; in sunxi_mmc_setup()
335 phase->offset = 8; in sunxi_mmc_setup()
337 phase->offset = 20; in sunxi_mmc_setup()
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/linux-6.3-rc2/drivers/hwmon/pmbus/
A Dmp2888.c98 ret = pmbus_read_word_data(client, page, phase, reg); in mp2888_read_phase()
102 if (!((phase + 1) % 2)) in mp2888_read_phase()
132 switch (phase) { in mp2888_read_phases()
162 ret = pmbus_read_word_data(client, page, phase, reg); in mp2888_read_word_data()
174 ret = pmbus_read_word_data(client, page, phase, reg); in mp2888_read_word_data()
184 if (phase != 0xff) in mp2888_read_word_data()
185 return mp2888_read_phases(client, data, page, phase); in mp2888_read_word_data()
187 ret = pmbus_read_word_data(client, page, phase, reg); in mp2888_read_word_data()
198 ret = pmbus_read_word_data(client, page, phase, reg); in mp2888_read_word_data()
211 ret = pmbus_read_word_data(client, page, phase, reg); in mp2888_read_word_data()
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A Dmp2975.c122 int page, int phase, u8 reg) in mp2975_read_phase() argument
130 if (!((phase + 1) % MP2975_PAGE_NUM)) in mp2975_read_phase()
163 int page, int phase) in mp2975_read_phases() argument
168 switch (phase) { in mp2975_read_phases()
170 ret = mp2975_read_phase(client, data, page, phase, in mp2975_read_phases()
174 ret = mp2975_read_phase(client, data, page, phase, in mp2975_read_phases()
185 switch (phase) { in mp2975_read_phases()
218 int phase, int reg) in mp2975_read_word_data() argument
244 ret = mp2975_read_word_helper(client, page, phase, in mp2975_read_word_data()
254 ret = mp2975_read_word_helper(client, page, phase, in mp2975_read_word_data()
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A Dir35221.c25 int phase, int reg) in ir35221_read_word_data() argument
31 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
35 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
39 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
43 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
47 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
51 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
55 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
59 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
A Dlt7182s.c35 static int lt7182s_read_word_data(struct i2c_client *client, int page, int phase, int reg) in lt7182s_read_word_data() argument
42 ret = pmbus_read_word_data(client, page, phase, MFR_READ_ITH); in lt7182s_read_word_data()
44 ret = pmbus_read_word_data(client, 0, phase, MFR_READ_EXTVCC); in lt7182s_read_word_data()
47 ret = pmbus_read_word_data(client, page, phase, MFR_IOUT_PEAK); in lt7182s_read_word_data()
50 ret = pmbus_read_word_data(client, page, phase, MFR_VOUT_PEAK); in lt7182s_read_word_data()
53 ret = pmbus_read_word_data(client, page, phase, MFR_VIN_PEAK); in lt7182s_read_word_data()
56 ret = pmbus_read_word_data(client, page, phase, MFR_TEMPERATURE_1_PEAK); in lt7182s_read_word_data()
A Dltc3815.c73 int phase, int reg) in ltc3815_read_word_data() argument
79 ret = pmbus_read_word_data(client, page, phase, in ltc3815_read_word_data()
83 ret = pmbus_read_word_data(client, page, phase, in ltc3815_read_word_data()
87 ret = pmbus_read_word_data(client, page, phase, in ltc3815_read_word_data()
91 ret = pmbus_read_word_data(client, page, phase, in ltc3815_read_word_data()
95 ret = pmbus_read_word_data(client, page, phase, in ltc3815_read_word_data()
/linux-6.3-rc2/drivers/char/
A Dppdev.c397 pp->saved_state.phase = info->phase; in pp_do_ioctl()
399 info->phase = pp->state.phase; in pp_do_ioctl()
458 pp->state.phase = phase; in pp_do_ioctl()
461 pp->pdev->port->ieee1284.phase = phase; in pp_do_ioctl()
472 phase = pp->state.phase; in pp_do_ioctl()
544 pp->state.phase = info->phase; in pp_do_ioctl()
546 info->phase = pp->saved_state.phase; in pp_do_ioctl()
722 pp->saved_state.phase = info->phase; in pp_release()
724 info->phase = pp->state.phase; in pp_release()
741 pp->state.phase = info->phase; in pp_release()
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/linux-6.3-rc2/drivers/gpu/drm/imx/dcss/
A Ddcss-scaler.c178 int phase; in dcss_scaler_gaussian_filter() local
183 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
184 coef[phase][0] = 0; in dcss_scaler_gaussian_filter()
185 coef[phase][PSC_NUM_TAPS - 1] = 0; in dcss_scaler_gaussian_filter()
232 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
237 sum += coef[phase][i]; in dcss_scaler_gaussian_filter()
239 ll_temp = coef[phase][i]; in dcss_scaler_gaussian_filter()
243 coef[phase][i] = (int)ll_temp; in dcss_scaler_gaussian_filter()
589 int i, phase; in dcss_scaler_program_5_coef_set() local
624 int i, phase; in dcss_scaler_program_7_coef_set() local
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/linux-6.3-rc2/lib/zstd/compress/
A Dzstd_cwksp.h153 ZSTD_cwksp_alloc_phase_e phase; member
275 assert(phase >= ws->phase); in ZSTD_cwksp_internal_advance_phase()
276 if (phase > ws->phase) { in ZSTD_cwksp_internal_advance_phase()
278 if (ws->phase < ZSTD_cwksp_alloc_buffers && in ZSTD_cwksp_internal_advance_phase()
279 phase >= ZSTD_cwksp_alloc_buffers) { in ZSTD_cwksp_internal_advance_phase()
284 if (ws->phase < ZSTD_cwksp_alloc_aligned && in ZSTD_cwksp_internal_advance_phase()
285 phase >= ZSTD_cwksp_alloc_aligned) { in ZSTD_cwksp_internal_advance_phase()
306 ws->phase = phase; in ZSTD_cwksp_internal_advance_phase()
483 if (ws->phase > ZSTD_cwksp_alloc_buffers) { in ZSTD_cwksp_clear()
484 ws->phase = ZSTD_cwksp_alloc_buffers; in ZSTD_cwksp_clear()
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/linux-6.3-rc2/Documentation/devicetree/bindings/mmc/
A Dsamsung,exynos-dw-mshc.yaml54 - description: CIU clock phase shift value for tx mode
57 - description: CIU clock phase shift value for rx mode
61 The value of CUI clock phase shift value in transmit mode and CIU clock
62 phase shift value in receive mode for double data rate mode operation.
68 - description: CIU clock phase shift value for tx mode
71 - description: CIU clock phase shift value for rx mode
75 The value of CIU TX and RX clock phase shift value for HS400 mode
78 - valid value for tx phase shift and rx phase shift is 0 to 7.
82 phase shift clocks should be 0.
88 - description: CIU clock phase shift value for tx mode
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/linux-6.3-rc2/drivers/parport/
A Dieee1284_ops.c171 port->ieee1284.phase = IEEE1284_PH_REV_DATA; in parport_ieee1284_read_nibble()
345 port->ieee1284.phase = IEEE1284_PH_REV_IDLE; in ecp_forward_to_reverse()
374 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in ecp_reverse_to_forward()
401 if (port->ieee1284.phase != IEEE1284_PH_FWD_IDLE) in parport_ieee1284_ecp_write_data()
405 port->ieee1284.phase = IEEE1284_PH_FWD_DATA; in parport_ieee1284_ecp_write_data()
467 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_ieee1284_ecp_write_data()
489 if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) in parport_ieee1284_ecp_read_data()
493 port->ieee1284.phase = IEEE1284_PH_REV_DATA; in parport_ieee1284_ecp_read_data()
612 port->ieee1284.phase = IEEE1284_PH_REV_IDLE; in parport_ieee1284_ecp_read_data()
635 port->ieee1284.phase = IEEE1284_PH_FWD_DATA; in parport_ieee1284_ecp_write_addr()
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/linux-6.3-rc2/drivers/net/wwan/iosm/
A Diosm_ipc_imem_ops.c66 if (ipc_imem->phase != IPC_P_RUN) { in ipc_imem_sys_wwan_transmit()
142 enum ipc_phase phase; in ipc_imem_is_channel_active() local
145 phase = ipc_imem->phase; in ipc_imem_is_channel_active()
148 switch (phase) { in ipc_imem_is_channel_active()
170 channel->channel_id, phase); in ipc_imem_is_channel_active()
199 curr_phase = ipc_imem->phase; in ipc_imem_sys_port_close()
319 ipc_imem->phase == IPC_P_OFF_REQ) in ipc_imem_sys_cdev_write()
345 enum ipc_phase phase; in ipc_imem_sys_devlink_open() local
349 switch (phase) { in ipc_imem_sys_devlink_open()
525 ipc_imem->phase = IPC_P_PSI; in ipc_imem_sys_psi_transfer()
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A Diosm_ipc_imem.c632 old_phase = ipc_imem->phase; in ipc_imem_handle_irq()
644 switch (phase) { in ipc_imem_handle_irq()
750 if ((phase == IPC_P_PSI || phase == IPC_P_EBL) && in ipc_imem_handle_irq()
837 return ipc_imem->phase; in ipc_imem_phase_update_check()
893 ipc_imem->phase : in ipc_imem_phase_update()
899 switch (phase) { in ipc_imem_phase_get_string()
1243 ipc_imem->phase = IPC_P_OFF; in ipc_imem_cleanup()
1253 enum ipc_phase phase; in ipc_imem_config() local
1267 switch (phase) { in ipc_imem_config()
1298 phase); in ipc_imem_config()
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/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_dccg.c53 int phase; in dccg21_update_dpp_dto() local
67 phase = (req_dppclk + 9999) / 10000; in dccg21_update_dpp_dto()
69 if (phase > modulo) { in dccg21_update_dpp_dto()
74 phase = modulo; in dccg21_update_dpp_dto()
85 phase = 10; in dccg21_update_dpp_dto()
89 DPPCLK0_DTO_PHASE, phase, in dccg21_update_dpp_dto()
/linux-6.3-rc2/drivers/char/ipmi/
A Dkcs_bmc_cdev_ipmi.c76 enum kcs_ipmi_phases phase; member
133 priv->phase = KCS_PHASE_ERROR; in kcs_bmc_ipmi_force_abort()
145 switch (priv->phase) { in kcs_bmc_ipmi_handle_data()
147 priv->phase = KCS_PHASE_WRITE_DATA; in kcs_bmc_ipmi_handle_data()
165 priv->phase = KCS_PHASE_WRITE_DONE; in kcs_bmc_ipmi_handle_data()
187 priv->phase = KCS_PHASE_IDLE; in kcs_bmc_ipmi_handle_data()
198 priv->phase = KCS_PHASE_ABORT_ERROR2; in kcs_bmc_ipmi_handle_data()
205 priv->phase = KCS_PHASE_IDLE; in kcs_bmc_ipmi_handle_data()
224 priv->phase = KCS_PHASE_WRITE_START; in kcs_bmc_ipmi_handle_cmd()
368 priv->phase = KCS_PHASE_WAIT_READ; in kcs_bmc_ipmi_read()
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/linux-6.3-rc2/include/trace/events/
A Dclk.h200 TP_PROTO(struct clk_core *core, int phase),
202 TP_ARGS(core, phase),
206 __field( int, phase )
211 __entry->phase = phase;
214 TP_printk("%s %d", __get_str(name), (int)__entry->phase)
219 TP_PROTO(struct clk_core *core, int phase),
221 TP_ARGS(core, phase)
226 TP_PROTO(struct clk_core *core, int phase),
228 TP_ARGS(core, phase)
/linux-6.3-rc2/drivers/scsi/pcmcia/
A Dnsp_cs.c371 unsigned char phase, arbit; in nsphw_start_selection() local
376 if(phase != BUSMON_BUS_FREE) { in nsphw_start_selection()
383 scsi_pointer->phase = PH_ARBSTART; in nsphw_start_selection()
403 scsi_pointer->phase = PH_SELSTART; in nsphw_start_selection()
548 unsigned char phase, i_src; in nsp_expect_signal() local
555 if (phase == 0xff) { in nsp_expect_signal()
564 if ((phase & mask) != 0 && (phase & BUSMON_PHASE_MASK) == current_phase) { in nsp_expect_signal()
602 if (phase & BUSMON_IO) { in nsp_xfer()
641 scsi_pointer->phase = PH_DATA; in nsp_dataphase_bypass()
1085 switch (scsi_pointer->phase) { in nspintr()
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/linux-6.3-rc2/Documentation/devicetree/bindings/spi/
A Dsamsung,spi-peripheral-props.yaml23 The sampling phase shift to be applied on the miso line (to account
25 - 0: No phase shift.
26 - 1: 90 degree phase shift sampling.
27 - 2: 180 degree phase shift sampling.
28 - 3: 270 degree phase shift sampling.
/linux-6.3-rc2/drivers/mmc/core/
A Dhost.c224 struct mmc_clk_phase *phase) in mmc_of_parse_timing_phase() argument
230 phase->valid = !rc; in mmc_of_parse_timing_phase()
231 if (phase->valid) { in mmc_of_parse_timing_phase()
232 phase->in_deg = degrees[0]; in mmc_of_parse_timing_phase()
233 phase->out_deg = degrees[1]; in mmc_of_parse_timing_phase()
243 &map->phase[MMC_TIMING_LEGACY]); in mmc_of_parse_clk_phase()
245 &map->phase[MMC_TIMING_MMC_HS]); in mmc_of_parse_clk_phase()
247 &map->phase[MMC_TIMING_SD_HS]); in mmc_of_parse_clk_phase()
249 &map->phase[MMC_TIMING_UHS_SDR12]); in mmc_of_parse_clk_phase()
251 &map->phase[MMC_TIMING_UHS_SDR25]); in mmc_of_parse_clk_phase()
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/linux-6.3-rc2/drivers/leds/trigger/
A Dledtrig-heartbeat.c27 unsigned int phase; member
52 switch (heartbeat_data->phase) { in led_heartbeat_function()
65 heartbeat_data->phase++; in led_heartbeat_function()
71 heartbeat_data->phase++; in led_heartbeat_function()
77 heartbeat_data->phase++; in led_heartbeat_function()
84 heartbeat_data->phase = 0; in led_heartbeat_function()
140 heartbeat_data->phase = 0; in heartbeat_trig_activate()
/linux-6.3-rc2/drivers/infiniband/hw/efa/
A Defa_com.c347 aq->sq.phase = !aq->sq.phase; in __efa_com_submit_admin_cmd()
438 u8 phase; in efa_com_handle_admin_completion() local
444 phase = aq->cq.phase; in efa_com_handle_admin_completion()
462 phase = !phase; in efa_com_handle_admin_completion()
469 aq->cq.phase = phase; in efa_com_handle_admin_completion()
843 phase = aenq->phase; in efa_com_aenq_intr_handler()
867 phase = !phase; in efa_com_aenq_intr_handler()
874 aenq->phase = phase; in efa_com_aenq_intr_handler()
1169 phase = eeq->phase; in efa_com_eq_comp_intr_handler()
1188 phase = !phase; in efa_com_eq_comp_intr_handler()
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/linux-6.3-rc2/drivers/scsi/
A DNCR5380.c765 p = ncmd->phase; in NCR5380_dma_complete()
1200 phase = PHASE_MSGOUT; in NCR5380_select()
1363 *phase = PHASE_UNKNOWN; in NCR5380_transfer_pio()
1365 if (!c || (*phase == p)) in NCR5380_transfer_pio()
1449 phase = PHASE_MSGOUT; in do_abort()
1489 unsigned char p = *phase; in NCR5380_transfer_dma()
1495 *phase = tmp; in NCR5380_transfer_dma()
1698 old_phase = phase; in NCR5380_information_transfer()
1738 switch (phase) { in NCR5380_information_transfer()
1916 phase = PHASE_MSGIN; in NCR5380_information_transfer()
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