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Searched refs:phy_write_mmd (Results 1 – 25 of 27) sorted by relevance

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/linux-6.3-rc2/drivers/net/phy/
A Dnxp-c45-tja11xx.c504 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_gpio_config()
763 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_EVENT_MSG_FILT, in nxp_c45_hwtstamp()
870 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, in nxp_c45_config_enable()
875 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_CONTROL, in nxp_c45_config_enable()
877 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL, in nxp_c45_config_enable()
910 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_IRQ_ACK, in nxp_c45_handle_interrupt()
1117 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, in nxp_c45_set_delays()
1127 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, in nxp_c45_set_delays()
1261 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 1); in nxp_c45_config_init()
1262 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 2); in nxp_c45_config_init()
[all …]
A Dmediatek-ge.c27 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); in mtk_gephy_config_init()
40 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff); in mtk_gephy_config_init()
43 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300); in mtk_gephy_config_init()
65 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404); in mt7531_phy_config_init()
66 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404); in mt7531_phy_config_init()
A Dintel-xway.c255 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, in xway_gphy_config_init()
259 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, in xway_gphy_config_init()
272 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, ledxh); in xway_gphy_config_init()
273 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, ledxl); in xway_gphy_config_init()
274 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, ledxh); in xway_gphy_config_init()
275 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, ledxl); in xway_gphy_config_init()
276 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); in xway_gphy_config_init()
277 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl); in xway_gphy_config_init()
A Ddp83869.c273 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
279 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
285 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
297 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
303 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
308 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
697 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, in dp83869_configure_mode()
732 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_configure_mode()
744 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_configure_mode()
765 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_configure_mode()
[all …]
A Ddp83tc811.c113 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA1, in dp83811_set_wol()
115 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA2, in dp83811_set_wol()
117 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA3, in dp83811_set_wol()
128 phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
131 phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
134 phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
148 return phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
A Ddp83td510.c57 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PHY_STS, in dp83td510_config_intr()
62 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
74 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
86 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PHY_STS, in dp83td510_config_intr()
A Dat803x.c461 phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], in at803x_set_wol()
1630 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); in qca83xx_config_init()
1633 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); in qca83xx_config_init()
1745 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, in qca808x_phy_fast_retrain_config()
1792 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, in qca808x_config_init()
1957 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); in qca808x_cable_test_start()
1958 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); in qca808x_cable_test_start()
1959 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); in qca808x_cable_test_start()
1960 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); in qca808x_cable_test_start()
1961 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); in qca808x_cable_test_start()
[all …]
A Ddp83822.c139 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1, in dp83822_set_wol()
141 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2, in dp83822_set_wol()
143 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3, in dp83822_set_wol()
154 phy_write_mmd(phydev, DP83822_DEVADDR, in dp83822_set_wol()
157 phy_write_mmd(phydev, DP83822_DEVADDR, in dp83822_set_wol()
160 phy_write_mmd(phydev, DP83822_DEVADDR, in dp83822_set_wol()
174 return phy_write_mmd(phydev, DP83822_DEVADDR, in dp83822_set_wol()
590 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value | in dp83822_resume()
A Dmicrel.c950 return phy_write_mmd(phydev, 2, reg, newval); in ksz9031_of_load_skew_values()
1192 return phy_write_mmd(phydev, 2, reg, newval); in ksz9131_of_load_skew_values()
3277 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, in lan8841_config_init()
3280 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, in lan8841_config_init()
3290 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, in lan8841_config_init()
3293 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, in lan8841_config_init()
3304 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, in lan8841_config_init()
3309 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, in lan8841_config_init()
3311 phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG, in lan8841_config_init()
3684 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL, in lan8841_ptp_settime64()
[all …]
A Ddp83867.c203 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1, in dp83867_set_wol()
205 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2, in dp83867_set_wol()
207 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3, in dp83867_set_wol()
216 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, in dp83867_set_wol()
218 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2, in dp83867_set_wol()
220 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3, in dp83867_set_wol()
242 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg); in dp83867_set_wol()
808 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); in dp83867_config_init()
817 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, in dp83867_config_init()
862 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val); in dp83867_config_init()
A Dbcm87xx.c69 ret = phy_write_mmd(phydev, devid, reg, val); in bcm87xx_of_reg_init()
155 err = phy_write_mmd(phydev, MDIO_MMD_PCS, in bcm87xx_config_intr()
159 err = phy_write_mmd(phydev, MDIO_MMD_PCS, in bcm87xx_config_intr()
A Dmarvell-88x2222.c81 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PORT_RST, in mv2222_soft_reset()
202 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
205 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
208 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
A Dphy-c45.c167 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); in genphy_c45_pma_setup_forced()
171 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); in genphy_c45_pma_setup_forced()
1259 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1267 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1299 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
A Dncn26000.c45 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR, in ncn26000_config_init()
A Daquantia_main.c298 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, in aqr_config_intr()
303 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, in aqr_config_intr()
308 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, in aqr_config_intr()
A Daquantia_hwmon.c79 return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp); in aqr_hwmon_set()
A Dmarvell10g.c265 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, in mv3310_hwmon_config()
1290 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1297 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1304 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
A Dadin1100.c145 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, in adin_set_powerdown_mode()
A Dbcm-phy-lib.c384 phy_write_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL, (u32)val); in bcm_phy_set_eee()
403 phy_write_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV, (u32)val); in bcm_phy_set_eee()
A Dmicrochip.c329 phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG, in lan88xx_config_init()
A Dadin.c296 return phy_write_mmd(phydev, MDIO_MMD_VEND1, in adin_config_rgmii_mode()
323 return phy_write_mmd(phydev, MDIO_MMD_VEND1, in adin_config_rmii_mode()
A Dphy-core.c643 int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val) in phy_write_mmd() function
653 EXPORT_SYMBOL(phy_write_mmd);
A Dmxl-gpy.c225 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO, in gpy_mbox_read()
233 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd); in gpy_mbox_read()
/linux-6.3-rc2/drivers/net/ethernet/realtek/
A Dr8169_phy_config.c580 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0000); in rtl8168e_1_hw_phy_config()
/linux-6.3-rc2/drivers/net/usb/
A Dlan78xx.c2251 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8010, buf); in lan8835_fixup()
2271 phy_write_mmd(phydev, MDIO_MMD_WIS, 4, 0x0077); in ksz9031rnx_fixup()
2273 phy_write_mmd(phydev, MDIO_MMD_WIS, 5, 0x7777); in ksz9031rnx_fixup()
2275 phy_write_mmd(phydev, MDIO_MMD_WIS, 8, 0x1FF); in ksz9031rnx_fixup()

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