| /linux-6.3-rc2/drivers/gpu/drm/i915/display/ |
| A D | intel_dp.h | 32 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
73 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
110 u32 pipe_bpp,
124 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp);
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| A D | intel_dp.c | 709 u32 pipe_bpp, in intel_dp_dsc_get_output_bpp() argument
1053 pipe_bpp, 64) >> 4; in intel_dp_mode_valid()
1494 int pipe_bpp; in intel_dp_dsc_compute_config() local
1506 pipe_bpp = pipe_config->pipe_bpp; in intel_dp_dsc_compute_config()
1514 if (pipe_bpp < 8 * 3) { in intel_dp_dsc_compute_config()
1525 pipe_config->pipe_bpp = pipe_bpp; in intel_dp_dsc_compute_config()
1548 pipe_bpp, in intel_dp_dsc_compute_config()
1604 pipe_config->pipe_bpp, in intel_dp_dsc_compute_config()
1612 pipe_config->pipe_bpp, in intel_dp_dsc_compute_config()
1694 pipe_config->pipe_bpp, in intel_dp_compute_link_config()
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| A D | g4x_hdmi.c | 43 if (crtc_state->pipe_bpp > 24) in intel_hdmi_prepare()
226 if (pipe_config->pipe_bpp > 24 && in ibx_enable_hdmi()
275 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
286 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
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| A D | intel_dp_mst.c | 116 crtc_state->pipe_bpp = bpp; in intel_dp_mst_find_vcpi_slots_for_bpp()
141 intel_link_compute_m_n(crtc_state->pipe_bpp, in intel_dp_mst_compute_link_config()
217 crtc_state->pipe_bpp); in intel_dp_dsc_mst_compute_link_config()
235 intel_link_compute_m_n(crtc_state->pipe_bpp, in intel_dp_dsc_mst_compute_link_config()
315 limits.max_bpp = min(pipe_config->pipe_bpp, 24); in intel_dp_mst_compute_config()
912 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); in intel_dp_mst_mode_valid_ctx() local
922 pipe_bpp, 64) >> 4; in intel_dp_mst_mode_valid_ctx()
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| A D | intel_lvds.c | 293 if (pipe_config->dither && pipe_config->pipe_bpp == 18) in intel_pre_enable_lvds()
436 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { in intel_lvds_compute_config()
439 pipe_config->pipe_bpp, lvds_bpp); in intel_lvds_compute_config()
440 pipe_config->pipe_bpp = lvds_bpp; in intel_lvds_compute_config()
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| A D | intel_fdi.c | 255 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
259 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, in ilk_fdi_compute_config()
266 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { in ilk_fdi_compute_config()
267 pipe_config->pipe_bpp -= 2*3; in ilk_fdi_compute_config()
270 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
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| A D | hsw_ips.c | 192 if (crtc_state->pipe_bpp > 24) in hsw_crtc_state_ips_capable()
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| A D | intel_hdmi.c | 942 static bool gcp_default_phase_possible(int pipe_bpp, in gcp_default_phase_possible() argument
947 switch (pipe_bpp) { in gcp_default_phase_possible()
1037 if (crtc_state->pipe_bpp > 24) in intel_hdmi_compute_gcp_infoframe()
1041 if (gcp_default_phase_possible(crtc_state->pipe_bpp, in intel_hdmi_compute_gcp_infoframe()
2086 bpc = max(crtc_state->pipe_bpp / 3, 8); in intel_hdmi_compute_bpc()
2134 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); in intel_hdmi_compute_clock()
2138 bpc, crtc_state->pipe_bpp); in intel_hdmi_compute_clock()
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| A D | intel_display.c | 3209 pipe_config->pipe_bpp = 18; in i9xx_get_pipe_config()
3212 pipe_config->pipe_bpp = 24; in i9xx_get_pipe_config()
3215 pipe_config->pipe_bpp = 30; in i9xx_get_pipe_config()
3627 pipe_config->pipe_bpp = 18; in ilk_get_pipe_config()
3630 pipe_config->pipe_bpp = 24; in ilk_get_pipe_config()
3633 pipe_config->pipe_bpp = 30; in ilk_get_pipe_config()
3636 pipe_config->pipe_bpp = 36; in ilk_get_pipe_config()
4903 crtc_state->pipe_bpp); in compute_sink_pipe_bpp()
4905 crtc_state->pipe_bpp = bpp; in compute_sink_pipe_bpp()
4930 crtc_state->pipe_bpp = bpp; in compute_baseline_pipe_bpp()
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| A D | intel_ddi.c | 369 switch (crtc_state->pipe_bpp) { in intel_ddi_set_dp_msa()
383 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_set_dp_msa()
460 switch (crtc_state->pipe_bpp) { in intel_ddi_transcoder_func_reg_val_get()
462 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_transcoder_func_reg_val_get()
3356 pipe_config->pipe_bpp = 18; in intel_ddi_read_func_ctl()
3359 pipe_config->pipe_bpp = 24; in intel_ddi_read_func_ctl()
3362 pipe_config->pipe_bpp = 30; in intel_ddi_read_func_ctl()
3365 pipe_config->pipe_bpp = 36; in intel_ddi_read_func_ctl()
3467 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); in intel_ddi_get_config()
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| A D | intel_crtc_state_dump.c | 187 pipe_config->pipe_bpp, pipe_config->dither); in intel_crtc_state_dump()
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| A D | intel_crt.c | 438 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { in hsw_crt_compute_config()
444 pipe_config->pipe_bpp = 24; in hsw_crt_compute_config()
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| A D | icl_dsi.c | 1577 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); in gen11_dsi_get_config()
1622 if (crtc_state->pipe_bpp < 8 * 3) in gen11_dsi_dsc_compute_config()
1689 pipe_config->pipe_bpp = 24; in gen11_dsi_compute_config()
1691 pipe_config->pipe_bpp = 18; in gen11_dsi_compute_config()
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| A D | vlv_dsi.c | 300 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
302 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
1133 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); in bxt_dsi_get_pipe_config()
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| A D | intel_panel.c | 611 if (DISPLAY_VER(dev_priv) < 4 && crtc_state->pipe_bpp == 18) in gmch_panel_fitting()
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| A D | intel_audio.c | 289 if (crtc_state->pipe_bpp == 36) { in audio_config_hdmi_get_n()
292 } else if (crtc_state->pipe_bpp == 30) { in audio_config_hdmi_get_n()
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| A D | intel_modeset_setup.c | 135 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; in intel_modeset_update_connector_atomic_state()
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| A D | intel_vdsc.c | 471 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; in intel_dsc_compute_params()
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| A D | intel_display_debugfs.c | 877 str_yes_no(crtc_state->dither), crtc_state->pipe_bpp); in intel_crtc_info()
1913 seq_printf(m, "Current: %u\n", crtc_state->pipe_bpp / 3); in i915_current_bpc_show()
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| A D | intel_display_types.h | 1141 int pipe_bpp; member
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| A D | intel_psr.c | 918 if (crtc_state->pipe_bpp > max_bpp) { in intel_psr2_config_valid()
921 crtc_state->pipe_bpp, max_bpp); in intel_psr2_config_valid()
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| A D | g4x_dp.c | 400 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); in intel_dp_get_config()
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| A D | intel_tv.c | 1212 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()
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| A D | intel_bios.c | 3506 crtc_state->pipe_bpp = bpc * 3; in fill_dsc()
3508 crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp, in fill_dsc()
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| A D | intel_sdvo.c | 1353 pipe_config->pipe_bpp = 8*3; in intel_sdvo_compute_config()
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