| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | display_rq_dlg_calc_32.c | 47 const unsigned int pipe_idx) in dml32_rq_dlg_get_rq_reg() argument
132 pipe_idx); in dml32_rq_dlg_get_rq_reg()
141 num_pipes, pipe_idx); in dml32_rq_dlg_get_rq_reg()
164 pipe_idx); in dml32_rq_dlg_get_rq_reg()
166 pipe_idx); in dml32_rq_dlg_get_rq_reg()
211 const unsigned int pipe_idx) in dml32_rq_dlg_get_dlg_reg() argument
289 pipe_idx); // From VBA in dml32_rq_dlg_get_dlg_reg()
384 pipe_idx) * refclk_freq_in_mhz; // From VBA in dml32_rq_dlg_get_dlg_reg()
393 pipe_idx) * refclk_freq_in_mhz; // From VBA in dml32_rq_dlg_get_dlg_reg()
403 pipe_idx) * refclk_freq_in_mhz; // From VBA in dml32_rq_dlg_get_dlg_reg()
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| A D | dcn32_fpu.c | 337 pipe_idx++; in dcn32_helper_populate_phantom_dlg_params()
562 pipe_idx++; in dcn32_set_phantom_stream_timing()
726 pipe_idx++; in dcn32_assign_subvp_pipe()
1063 pipe_idx++; in subvp_validate_static_schedulability()
1419 pipe_idx++; in dcn32_calculate_dlg_params()
1459 pipe_idx++; in dcn32_calculate_dlg_params()
1512 int pipe_idx = sec_pipe->pipe_idx; in dcn32_split_stream_for_mpc_or_odm() local
1540 sec_pipe->pipe_idx = pipe_idx; in dcn32_split_stream_for_mpc_or_odm()
1683 pipe_idx++; in dcn32_internal_validate_bw()
1771 pipe_idx++; in dcn32_internal_validate_bw()
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| A D | display_rq_dlg_calc_32.h | 48 const unsigned int pipe_idx);
68 const unsigned int pipe_idx);
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | display_rq_dlg_calc_314.c | 941 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params() argument
952 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
953 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
954 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml_rq_dlg_get_dlg_params()
955 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
957 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
1211 unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx]; in dml_rq_dlg_get_dlg_params()
1692 const unsigned int pipe_idx, in dml314_rq_dlg_get_dlg_reg() argument
1716 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); in dml314_rq_dlg_get_dlg_reg()
1722 pipe_idx, in dml314_rq_dlg_get_dlg_reg()
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| A D | display_rq_dlg_calc_314.h | 63 const unsigned int pipe_idx,
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_rq_dlg_calc_31.c | 856 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params() argument
867 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
868 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
869 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
871 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
1097 unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx]; in dml_rq_dlg_get_dlg_params()
1577 const unsigned int pipe_idx, in dml31_rq_dlg_get_dlg_reg() argument
1601 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); in dml31_rq_dlg_get_dlg_reg()
1602 dml_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe); in dml31_rq_dlg_get_dlg_reg()
1607 pipe_idx, in dml31_rq_dlg_get_dlg_reg()
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| A D | dcn31_fpu.c | 486 int i, pipe_idx, active_hubp_count = 0; in dcn31_calculate_wm_and_dlg_fp() local
527 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
534 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
535 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn31_calculate_wm_and_dlg_fp()
538 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
539 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
541 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn31_calculate_wm_and_dlg_fp()
542 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn31_calculate_wm_and_dlg_fp()
543 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn31_calculate_wm_and_dlg_fp()
544 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn31_calculate_wm_and_dlg_fp()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_resource.c | 1333 int pipe_idx) in dcn20_acquire_dsc() argument
1344 *dsc = pool->dscs[pipe_idx]; in dcn20_acquire_dsc()
1489 int pipe_idx = next_odm_pipe->pipe_idx; in dcn20_split_stream_for_odm() local
1494 next_odm_pipe->pipe_idx = pipe_idx; in dcn20_split_stream_for_odm()
1573 int pipe_idx = secondary_pipe->pipe_idx; in dcn20_split_stream_for_mpc() local
1579 secondary_pipe->pipe_idx = pipe_idx; in dcn20_split_stream_for_mpc()
1926 pipe_idx++; in dcn20_validate_apply_pipe_split_flags()
2033 pipe_idx++; in dcn20_validate_apply_pipe_split_flags()
2087 pipe_idx++; in dcn20_fast_validate_bw()
2096 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; in dcn20_fast_validate_bw()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| A D | dcn301_fpu.c | 420 int i, pipe_idx; in dcn301_calculate_wm_and_dlg_fp() local
455 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn301_calculate_wm_and_dlg_fp()
459 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn301_calculate_wm_and_dlg_fp()
460 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn301_calculate_wm_and_dlg_fp()
463 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn301_calculate_wm_and_dlg_fp()
464 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn301_calculate_wm_and_dlg_fp()
466 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn301_calculate_wm_and_dlg_fp()
467 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn301_calculate_wm_and_dlg_fp()
468 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn301_calculate_wm_and_dlg_fp()
469 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn301_calculate_wm_and_dlg_fp()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_rq_dlg_calc_30.c | 895 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params() argument
908 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml_rq_dlg_get_dlg_params()
1220 unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx]; in dml_rq_dlg_get_dlg_params()
1231 pipe_idx, in dml_rq_dlg_get_dlg_params()
1235 pipe_idx, in dml_rq_dlg_get_dlg_params()
1255 pipe_idx); in dml_rq_dlg_get_dlg_params()
1259 pipe_idx); in dml_rq_dlg_get_dlg_params()
1747 const unsigned int pipe_idx, in dml30_rq_dlg_get_dlg_reg() argument
1777 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); in dml30_rq_dlg_get_dlg_reg()
1782 pipe_idx, in dml30_rq_dlg_get_dlg_reg()
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| A D | dcn30_fpu.c | 384 int i, pipe_idx; in dcn30_fpu_calculate_wm_and_dlg() local
504 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_fpu_calculate_wm_and_dlg()
508 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_fpu_calculate_wm_and_dlg()
509 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn30_fpu_calculate_wm_and_dlg()
512 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
513 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
515 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn30_fpu_calculate_wm_and_dlg()
516 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn30_fpu_calculate_wm_and_dlg()
517 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn30_fpu_calculate_wm_and_dlg()
518 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn30_fpu_calculate_wm_and_dlg()
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| A D | display_rq_dlg_calc_30.h | 62 const unsigned int pipe_idx,
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_rq_dlg_calc_21.c | 833 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params() argument
842 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
843 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml_rq_dlg_get_dlg_params()
844 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
846 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
1153 pipe_idx); in dml_rq_dlg_get_dlg_params()
1158 pipe_idx); in dml_rq_dlg_get_dlg_params()
1663 const unsigned int pipe_idx, in dml21_rq_dlg_get_dlg_reg() argument
1696 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); in dml21_rq_dlg_get_dlg_reg()
1702 pipe_idx, in dml21_rq_dlg_get_dlg_reg()
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| A D | display_rq_dlg_calc_21.h | 66 const unsigned int pipe_idx,
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_resource.c | 1501 if (pipe_idx >= 0) in dc_add_plane_to_context()
1558 (free_pipe->pipe_idx != prev_right_head->bottom_pipe->pipe_idx)) { in dc_add_plane_to_context()
1563 (free_pipe->pipe_idx == prev_left_head->bottom_pipe->pipe_idx)) { in dc_add_plane_to_context()
1612 (free_pipe->pipe_idx != prev_right_head->bottom_pipe->pipe_idx)) { in dc_add_plane_to_context()
2472 int pipe_idx = -1; in resource_map_pool_resources() local
2483 if (pipe_idx < 0) in resource_map_pool_resources()
2488 if (pipe_idx < 0) in resource_map_pool_resources()
2492 if (pipe_idx < 0) in resource_map_pool_resources()
3891 uint8_t pipe_idx) in reset_sync_context_for_pipe() argument
4000 int pipe_idx = sec_pipe->pipe_idx; in dc_resource_acquire_secondary_pipe_for_mpc_odm() local
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_rq_dlg_calc_20v2.c | 49 const unsigned int pipe_idx,
787 const unsigned int pipe_idx, in dml20v2_rq_dlg_get_dlg_params() argument
797 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml20v2_rq_dlg_get_dlg_params()
798 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20v2_rq_dlg_get_dlg_params()
800 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml20v2_rq_dlg_get_dlg_params()
1105 pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
1109 pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
1555 const unsigned int pipe_idx, in dml20v2_rq_dlg_get_dlg_reg() argument
1585 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); in dml20v2_rq_dlg_get_dlg_reg()
1590 pipe_idx, in dml20v2_rq_dlg_get_dlg_reg()
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| A D | display_rq_dlg_calc_20.c | 49 const unsigned int pipe_idx,
787 const unsigned int pipe_idx, in dml20_rq_dlg_get_dlg_params() argument
797 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml20_rq_dlg_get_dlg_params()
798 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20_rq_dlg_get_dlg_params()
800 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml20_rq_dlg_get_dlg_params()
1104 pipe_idx); in dml20_rq_dlg_get_dlg_params()
1108 pipe_idx); in dml20_rq_dlg_get_dlg_params()
1554 const unsigned int pipe_idx, in dml20_rq_dlg_get_dlg_reg() argument
1584 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); in dml20_rq_dlg_get_dlg_reg()
1589 pipe_idx, in dml20_rq_dlg_get_dlg_reg()
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| A D | dcn20_fpu.c | 1045 int i, pipe_idx; in dcn20_calculate_dlg_params() local
1103 pipe_idx++; in dcn20_calculate_dlg_params()
1128 pipe_idx, in dcn20_calculate_dlg_params()
1135 &pipes[pipe_idx].pipe); in dcn20_calculate_dlg_params()
1136 pipe_idx++; in dcn20_calculate_dlg_params()
1625 int pipe_cnt, i, pipe_idx; in dcn20_calculate_wm() local
1639 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) in dcn20_calculate_wm()
1644 pipe_idx++; in dcn20_calculate_wm()
2120 int pipe_cnt, i, pipe_idx; in dcn21_calculate_wm() local
2139 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) in dcn21_calculate_wm()
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| A D | display_rq_dlg_calc_20.h | 66 const unsigned int pipe_idx,
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| A D | display_rq_dlg_calc_20v2.h | 66 const unsigned int pipe_idx,
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_mode_lib.h | 58 const unsigned int pipe_idx,
76 const unsigned int pipe_idx);
81 const unsigned int pipe_idx);
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce60/ |
| A D | dce60_hw_sequencer.c | 52 uint32_t *pipe_idx) in dce60_should_enable_fbc() argument
79 if (pipe_ctx->pipe_idx != underlay_idx) { in dce60_should_enable_fbc()
80 *pipe_idx = i; in dce60_should_enable_fbc()
118 uint32_t pipe_idx = 0; in dce60_enable_fbc() local
120 if (dce60_should_enable_fbc(dc, context, &pipe_idx)) { in dce60_enable_fbc()
124 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; in dce60_enable_fbc()
349 pipe_ctx->pipe_idx, in dce60_program_front_end_for_pipe()
370 pipe_ctx->pipe_idx, in dce60_program_front_end_for_pipe()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_resource.c | 1548 int pipe_idx = sec_pipe->pipe_idx; in dcn30_split_stream_for_mpc_or_odm() local
1553 sec_pipe->pipe_idx = pipe_idx; in dcn30_split_stream_for_mpc_or_odm()
1613 pipe->pipe_idx = old_index; in dcn30_find_split_pipe()
1622 pipe->pipe_idx = i; in dcn30_find_split_pipe()
1637 pipe->pipe_idx = i; in dcn30_find_split_pipe()
1659 int pipe_cnt, i, pipe_idx, vlevel; in dcn30_internal_validate_bw() local
1735 pipe_idx++; in dcn30_internal_validate_bw()
1795 pipe_idx++; in dcn30_internal_validate_bw()
1825 newly_split[hsplit_pipe->pipe_idx] = true; in dcn30_internal_validate_bw()
1846 newly_split[pipe_4to1->pipe_idx] = true; in dcn30_internal_validate_bw()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/ |
| A D | dc_dmub_srv.c | 544 pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx; in populate_subvp_cmd_vblank_pipe_info()
641 pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->pipe_idx; in populate_subvp_cmd_pipe_info()
683 pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->pipe_idx; in populate_subvp_cmd_pipe_info()
711 uint32_t i, pipe_idx; in dc_dmub_setup_subvp_dmub_command() local
739 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dc_dmub_setup_subvp_dmub_command()
759 pipe_idx++; in dc_dmub_setup_subvp_dmub_command()
955 payload->pipe_idx = p_idx; in dc_build_cursor_update_payload0()
980 pl->position_cfg.pipe_idx = p_idx; in dc_build_cursor_position_update_payload0()
1008 struct pipe_ctx *pCtx, uint8_t pipe_idx) in dc_send_update_cursor_info_to_dmu() argument
1035 dc_build_cursor_update_payload0(pCtx, pipe_idx, &update_cursor_info->payload0); in dc_send_update_cursor_info_to_dmu()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn21/ |
| A D | dcn21_resource.c | 819 int pipe_cnt, i, pipe_idx, vlevel; in dcn21_fast_validate_bw() local
863 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
872 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn21_fast_validate_bw()
880 pipe_idx++; in dcn21_fast_validate_bw()
887 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
894 pipe_idx++; in dcn21_fast_validate_bw()
896 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
903 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; in dcn21_fast_validate_bw()
920 …djust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true); in dcn21_fast_validate_bw()
924 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
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