| /linux-6.3-rc2/drivers/gpu/drm/i915/ |
| A D | i915_pci.c | 45 #define NO_DISPLAY .__runtime.pipe_mask = 0
177 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
199 .__runtime.pipe_mask = BIT(PIPE_A), \
242 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
333 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
387 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
418 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
471 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
535 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
630 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
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| A D | intel_device_info.c | 459 runtime->pipe_mask = 0; in intel_device_info_runtime_init()
464 runtime->pipe_mask &= ~BIT(PIPE_C); in intel_device_info_runtime_init()
471 runtime->pipe_mask &= ~BIT(PIPE_A); in intel_device_info_runtime_init()
476 runtime->pipe_mask &= ~BIT(PIPE_B); in intel_device_info_runtime_init()
480 runtime->pipe_mask &= ~BIT(PIPE_C); in intel_device_info_runtime_init()
486 runtime->pipe_mask &= ~BIT(PIPE_D); in intel_device_info_runtime_init()
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| A D | i915_irq.h | 70 u8 pipe_mask);
72 u8 pipe_mask);
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| A D | intel_device_info.h | 251 u8 pipe_mask; member
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| A D | i915_drv.h | 911 #define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask))
913 #define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0)
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| A D | i915_irq.c | 2776 u8 pipe_mask) in gen8_irq_power_well_post_enable() argument
2791 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_post_enable()
2800 u8 pipe_mask) in gen8_irq_power_well_pre_disable() argument
2812 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_pre_disable()
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| /linux-6.3-rc2/drivers/gpu/drm/i915/display/ |
| A D | intel_dpll_mgr.c | 233 if (drm_WARN_ON(&dev_priv->drm, !(pll->state.pipe_mask & pipe_mask)) || in intel_enable_shared_dpll()
237 pll->active_mask |= pipe_mask; in intel_enable_shared_dpll()
293 pll->active_mask &= ~pipe_mask; in intel_disable_shared_dpll()
337 shared_dpll[i].pipe_mask, in intel_find_shared_dpll()
366 if (shared_dpll[id].pipe_mask == 0) in intel_reference_shared_dpll()
4370 pll->state.pipe_mask = 0; in readout_dpll_hw_state()
4459 u8 pipe_mask; in verify_single_dpll_state() local
4486 pipe_mask = BIT(crtc->pipe); in verify_single_dpll_state()
4497 I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask), in verify_single_dpll_state()
4499 pipe_mask, pll->state.pipe_mask); in verify_single_dpll_state()
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| A D | intel_ddi.c | 742 *pipe_mask = 0; in intel_ddi_get_encoder_pipes()
764 *pipe_mask = BIT(PIPE_A); in intel_ddi_get_encoder_pipes()
767 *pipe_mask = BIT(PIPE_B); in intel_ddi_get_encoder_pipes()
809 *pipe_mask |= BIT(p); in intel_ddi_get_encoder_pipes()
812 if (!*pipe_mask) in intel_ddi_get_encoder_pipes()
821 *pipe_mask); in intel_ddi_get_encoder_pipes()
822 *pipe_mask = BIT(ffs(*pipe_mask) - 1); in intel_ddi_get_encoder_pipes()
850 u8 pipe_mask; in intel_ddi_get_hw_state() local
855 if (is_mst || !pipe_mask) in intel_ddi_get_hw_state()
2004 u8 pipe_mask; in intel_ddi_sanitize_encoder_pll_mapping() local
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| A D | intel_display.h | 228 for_each_if(RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
284 #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \ argument
288 for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
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| A D | g4x_hdmi.c | 610 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_hdmi_init()
612 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init()
614 intel_encoder->pipe_mask = ~0; in g4x_hdmi_init()
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| A D | intel_dp.c | 4037 u8 *pipe_mask) in intel_dp_prep_link_retrain() argument
4044 *pipe_mask = 0; in intel_dp_prep_link_retrain()
4078 *pipe_mask |= BIT(crtc->pipe); in intel_dp_prep_link_retrain()
4083 *pipe_mask = 0; in intel_dp_prep_link_retrain()
4102 u8 pipe_mask; in intel_dp_retrain_link() local
4117 if (pipe_mask == 0) in intel_dp_retrain_link()
4169 u8 *pipe_mask) in intel_dp_prep_phy_test() argument
4176 *pipe_mask = 0; in intel_dp_prep_phy_test()
4207 *pipe_mask |= BIT(crtc->pipe); in intel_dp_prep_phy_test()
4220 u8 pipe_mask; in intel_dp_do_phy_test() local
[all …]
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| A D | intel_dpll_mgr.h | 248 u8 pipe_mask; member
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| A D | intel_lvds.c | 925 intel_encoder->pipe_mask = BIT(PIPE_B); in intel_lvds_init()
927 intel_encoder->pipe_mask = ~0; in intel_lvds_init()
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| A D | g4x_dp.c | 1367 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_dp_init()
1369 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_dp_init()
1371 intel_encoder->pipe_mask = ~0; in g4x_dp_init()
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| A D | intel_crt.c | 1038 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init()
1040 crt->base.pipe_mask = ~0; in intel_crt_init()
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| A D | intel_dvo.c | 517 encoder->pipe_mask = ~0; in intel_dvo_init()
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| A D | vlv_dsi.c | 1911 intel_encoder->pipe_mask = ~0; in vlv_dsi_init()
1913 intel_encoder->pipe_mask = BIT(PIPE_A); in vlv_dsi_init()
1915 intel_encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
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| A D | intel_display_types.h | 160 u8 pipe_mask; member
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| A D | intel_dp_mst.c | 1136 intel_encoder->pipe_mask = ~0; in intel_dp_create_fake_mst_encoder()
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| A D | intel_tv.c | 2012 intel_encoder->pipe_mask = ~0; in intel_tv_init()
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| A D | intel_display_debugfs.c | 948 pll->state.pipe_mask, pll->active_mask, in i915_shared_dplls_info()
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| A D | icl_dsi.c | 2030 encoder->pipe_mask = ~0; in icl_dsi_init()
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| A D | intel_sdvo.c | 3011 intel_sdvo->base.pipe_mask = ~0; in intel_sdvo_output_setup()
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| A D | intel_display.c | 3695 return pipes & RUNTIME_INFO(i915)->pipe_mask; in bigjoiner_pipes()
7826 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) in intel_encoder_possible_crtcs()
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| /linux-6.3-rc2/drivers/usb/renesas_usbhs/ |
| A D | common.c | 276 u16 pipe_mask = (u16)GENMASK(usbhs_get_dparam(priv, pipe_size), 0); in usbhs_xxxsts_clear() local
278 usbhs_write(priv, sts_reg, ~(1 << bit) & pipe_mask); in usbhs_xxxsts_clear()
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