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Searched refs:plane_res (Results 1 – 25 of 32) sorted by relevance

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/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce60/
A Ddce60_hw_sequencer.c247 pipe_ctx->plane_res.xfm, in dce60_program_scaler()
265 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, in dce60_program_scaler()
266 &pipe_ctx->plane_res.scl_data); in dce60_program_scaler()
299 (pipe_ctx->plane_res.xfm, &tbl_entry); in dce60_program_front_end_for_pipe()
310 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); in dce60_program_front_end_for_pipe()
329 pipe_ctx->plane_res.mi, in dce60_program_front_end_for_pipe()
373 pipe_ctx->plane_res.scl_data.viewport.x, in dce60_program_front_end_for_pipe()
374 pipe_ctx->plane_res.scl_data.viewport.y, in dce60_program_front_end_for_pipe()
377 pipe_ctx->plane_res.scl_data.recout.x, in dce60_program_front_end_for_pipe()
378 pipe_ctx->plane_res.scl_data.recout.y); in dce60_program_front_end_for_pipe()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/core/
A Ddc_resource.c912 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz; in calculate_scaling_ratios()
913 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; in calculate_scaling_ratios()
1180 if (pipe_ctx->plane_res.xfm != NULL) in resource_build_scaling_params()
1182 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); in resource_build_scaling_params()
1186 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); in resource_build_scaling_params()
1195 pipe_ctx->plane_res.xfm, in resource_build_scaling_params()
1196 &pipe_ctx->plane_res.scl_data, in resource_build_scaling_params()
1201 pipe_ctx->plane_res.dpp, in resource_build_scaling_params()
1202 &pipe_ctx->plane_res.scl_data, in resource_build_scaling_params()
1223 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height; in resource_build_scaling_params()
[all …]
A Ddc_stream.c387 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || in program_cursor_position()
389 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || in program_cursor_position()
390 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp)) in program_cursor_position()
709 hubp = pipe_ctx->plane_res.hubp; in dc_stream_set_dynamic_metadata()
A Ddc_hw_sequencer.c320 switch (pipe_ctx->plane_res.scl_data.format) { in get_surface_visual_confirm_color()
377 switch (top_pipe_ctx->plane_res.scl_data.format) { in get_hdr_visual_confirm_color()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_hw_sequencer.c1381 pipe_ctx->plane_res.xfm, in program_scaler()
1399 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, in program_scaler()
1839 pipe_ctx->plane_res.mi, in dce110_set_displaymarks()
1848 pipe_ctx->plane_res.mi, in dce110_set_displaymarks()
2403 pipe_ctx->plane_res.mi, in update_plane_addr()
2419 pipe_ctx->plane_res.mi); in dce110_update_pending_status()
2422 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; in dce110_update_pending_status()
2723 pipe_ctx->plane_res.mi, in dce110_program_front_end_for_pipe()
2797 pipe_ctx->plane_res.mi, in dce110_apply_ctx_for_surface()
2917 if (pipe_ctx->plane_res.ipp && in dce110_set_cursor_attribute()
[all …]
A Ddce110_resource.c1135 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; in dce110_acquire_underlay()
1137 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; in dce110_acquire_underlay()
1171 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, in dce110_acquire_underlay()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_hwseq.c269 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { in dcn20_program_triple_buffer()
271 pipe_ctx->plane_res.hubp, in dcn20_program_triple_buffer()
601 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); in dcn20_plane_atomic_disable()
615 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) in dcn20_disable_plane()
1155 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); in dcn20_enable_plane()
1158 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); in dcn20_enable_plane()
1218 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); in dcn20_enable_plane()
1421 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp in dcn20_detect_pipe_changes()
1426 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) in dcn20_detect_pipe_changes()
1584 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); in dcn20_update_dchubp_dpp()
[all …]
A Ddcn20_resource.c1495 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1497 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1499 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1518 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; in dcn20_split_stream_for_odm()
1535 sd = &next_odm_pipe->plane_res.scl_data; in dcn20_split_stream_for_odm()
1580 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc()
1819 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res)); in dcn20_merge_pipes_for_validate()
1844 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res)); in dcn20_merge_pipes_for_validate()
2190 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; in dcn20_acquire_idle_pipe_for_layer()
2191 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; in dcn20_acquire_idle_pipe_for_layer()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calcs.c412 switch (pipe->plane_res.scl_data.lb_params.depth) { in pipe_ctx_to_e2e_pipe_params()
949 + pipe->plane_res.scl_data.viewport.x; in dcn_validate_bandwidth()
951 + pipe->bottom_pipe->plane_res.scl_data.viewport.x; in dcn_validate_bandwidth()
955 - pipe->bottom_pipe->plane_res.scl_data.viewport.x; in dcn_validate_bandwidth()
958 - pipe->plane_res.scl_data.viewport.x; in dcn_validate_bandwidth()
961 + pipe->plane_res.scl_data.viewport.y; in dcn_validate_bandwidth()
963 + pipe->bottom_pipe->plane_res.scl_data.viewport.y; in dcn_validate_bandwidth()
967 - pipe->bottom_pipe->plane_res.scl_data.viewport.y; in dcn_validate_bandwidth()
970 - pipe->plane_res.scl_data.viewport.y; in dcn_validate_bandwidth()
973 + pipe->bottom_pipe->plane_res.scl_data.recout.width; in dcn_validate_bandwidth()
[all …]
A Ddce_calcs.c2827 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width); in populate_initial_data()
2829 data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height); in populate_initial_data()
2830 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
2831 data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps); in populate_initial_data()
2886 …data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.… in populate_initial_data()
2889 pipe[i].bottom_pipe->plane_res.scl_data.ratios.horz.value); in populate_initial_data()
2891 pipe[i].bottom_pipe->plane_res.scl_data.ratios.vert.value); in populate_initial_data()
2930 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width); in populate_initial_data()
2932 data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height); in populate_initial_data()
2933 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_hw_sequencer.c1272 pipe_ctx->plane_res.dpp, in dcn10_plane_atomic_disable()
1273 pipe_ctx->plane_res.hubp); in dcn10_plane_atomic_disable()
1277 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); in dcn10_plane_atomic_disable()
1288 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) in dcn10_disable_plane()
1748 pipe_ctx->plane_res.hubp, in dcn10_update_plane_addr()
2469 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); in dcn10_enable_plane()
2487 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); in dcn10_enable_plane()
2512 pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust); in dcn10_program_gamut_remap()
2539 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix); in dcn10_set_csc_adjustment_rgb_mpo_fix()
2568 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix); in dcn10_program_output_csc()
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A Ddcn10_resource.c1116 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; in dcn10_acquire_idle_pipe_for_layer()
1117 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; in dcn10_acquire_idle_pipe_for_layer()
1118 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn10_acquire_idle_pipe_for_layer()
1119 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn10_acquire_idle_pipe_for_layer()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_hwseq.c147 pipe_ctx->plane_res.hubp, in dcn201_update_plane_addr()
323 pipe_ctx->plane_res.hubp = hubp; in dcn201_init_hw()
324 pipe_ctx->plane_res.dpp = dpp; in dcn201_init_hw()
325 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn201_init_hw()
356 pipe_ctx->plane_res.hubp = NULL; in dcn201_init_hw()
392 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn201_plane_atomic_disconnect()
393 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn201_plane_atomic_disconnect()
437 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn201_update_mpcc()
578 pipe_ctx->plane_res.hubp, attributes); in dcn201_set_cursor_attribute()
580 pipe_ctx->plane_res.dpp, attributes); in dcn201_set_cursor_attribute()
[all …]
A Ddcn201_resource.c1022 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; in dcn201_acquire_idle_pipe_for_layer()
1023 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; in dcn201_acquire_idle_pipe_for_layer()
1024 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn201_acquire_idle_pipe_for_layer()
1025 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn201_acquire_idle_pipe_for_layer()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn32/
A Ddcn32_resource_helpers.c60 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn32_helper_calculate_mall_bytes_for_cursor()
154 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn32_merge_pipes_for_subvp()
168 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn32_merge_pipes_for_subvp()
A Ddcn32_hwseq.c412 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_mpc_shaper_3dlut()
413 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_mpc_shaper_3dlut()
448 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_mcm_luts()
449 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_mcm_luts()
498 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_input_transfer_func()
538 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_output_transfer_func()
578 struct hubp *hubp = pipe->plane_res.hubp; in dcn32_subvp_update_force_pstate()
595 struct hubp *hubp = pipe->plane_res.hubp; in dcn32_subvp_update_force_pstate()
615 struct hubp *hubp = pipe->plane_res.hubp; in dcn32_update_mall_sel()
679 struct hubp *hubp = pipe->plane_res.hubp; in dcn32_program_mall_pipe_config()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_trace.h386 const struct plane_resource *plane_res,
388 TP_ARGS(pipe_idx, plane_state, stream, plane_res, update_flags),
439 __entry->recout_x = plane_res->scl_data.recout.x;
440 __entry->recout_y = plane_res->scl_data.recout.y;
441 __entry->recout_w = plane_res->scl_data.recout.width;
442 __entry->recout_h = plane_res->scl_data.recout.height;
443 __entry->viewport_x = plane_res->scl_data.viewport.x;
444 __entry->viewport_y = plane_res->scl_data.viewport.y;
445 __entry->viewport_w = plane_res->scl_data.viewport.width;
446 __entry->viewport_h = plane_res->scl_data.viewport.height;
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/
A Ddc_trace.h31 pipe_ctx->stream, &pipe_ctx->plane_res, \
A Ddc_dmub_srv.c874 const struct scaler_data *scl_data = &pipe_ctx->plane_res.scl_data; in dc_can_pipe_disable_cursor()
890 r2 = test_pipe->plane_res.scl_data.recout; in dc_can_pipe_disable_cursor()
902 r2_half = split_pipe->plane_res.scl_data.recout; in dc_can_pipe_disable_cursor()
938 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dc_build_cursor_update_payload0()
1038 pCtx->plane_res.hubp, pCtx->plane_res.dpp); in dc_send_update_cursor_info_to_dmu()
1051 pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp); in dc_send_update_cursor_info_to_dmu()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_hwseq.c75 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut()
96 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_mpc_shaper_3dlut()
97 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_mpc_shaper_3dlut()
151 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_input_transfer_func()
193 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_output_transfer_func()
407 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dcn30_program_all_writeback_pipes_in_tree()
693 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn30_program_dmdata_engine()
A Ddcn30_resource.c1554 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1555 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1556 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1557 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1558 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1559 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dcn30_split_stream_for_mpc_or_odm()
1729 && memcmp(&mpo_pipe->plane_res.scl_data.recout, in dcn30_internal_validate_bw()
1730 &pipe->plane_res.scl_data.recout, in dcn30_internal_validate_bw()
1762 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn30_internal_validate_bw()
1777 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn30_internal_validate_bw()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
A Drv1_clk_mgr.c172 pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control( in ramp_up_dispclk_with_dpp()
173 pipe_ctx->plane_res.dpp, in ramp_up_dispclk_with_dpp()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce/
A Ddmub_psr.c347 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dmub_psr_copy_settings()
349 if (pipe_ctx->plane_res.dpp) in dmub_psr_copy_settings()
350 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; in dmub_psr_copy_settings()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c1389 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0; in dcn32_calculate_dlg_params()
1541 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; in dcn32_split_stream_for_mpc_or_odm()
1542 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; in dcn32_split_stream_for_mpc_or_odm()
1543 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; in dcn32_split_stream_for_mpc_or_odm()
1544 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; in dcn32_split_stream_for_mpc_or_odm()
1545 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; in dcn32_split_stream_for_mpc_or_odm()
1546 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dcn32_split_stream_for_mpc_or_odm()
1677 && memcmp(&mpo_pipe->plane_res.scl_data.recout, in dcn32_internal_validate_bw()
1678 &pipe->plane_res.scl_data.recout, in dcn32_internal_validate_bw()
1736 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn32_internal_validate_bw()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/inc/
A Dcore_types.h387 struct plane_resource plane_res; member

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