pll2_mult (reference) in projects: linux-6.3-rc2

Searched refs:pll2_mult (Results 1 – 6 of 6) sorted by relevance

/linux-6.3-rc2/arch/sh/kernel/cpu/sh2a/
A D	clock-sh7203.c	`25 static unsigned int pll2_mult; variable 29 clk->rate = pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] pll2_mult; in master_clk_init() 70 pll2_mult = 4; in arch_init_clk_ops() 72 pll2_mult = 2; in arch_init_clk_ops() 74 pll2_mult = 1; in arch_init_clk_ops()`
A D	clock-sh7201.c	`22 static unsigned int pll2_mult; variable 26 clk->rate = 10000000 * pll2_mult * in master_clk_init() 74 pll2_mult = 1; in arch_init_clk_ops() 76 pll2_mult = 2; in arch_init_clk_ops() 78 pll2_mult = 4; in arch_init_clk_ops()`
A D	clock-sh7206.c	`22 static unsigned int pll2_mult; variable 26 clk->rate = pll2_mult pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; in master_clk_init() 72 pll2_mult = 1; in arch_init_clk_ops() 74 pll2_mult = 2; in arch_init_clk_ops() 76 pll2_mult = 4; in arch_init_clk_ops()`
/linux-6.3-rc2/arch/sh/kernel/cpu/sh2/
A D	clock-sh7619.c	`21 static unsigned int pll2_mult; variable 25 clk->rate = pll2_mult pll1rate[(__raw_readw(FREQCR) >> 8) & 7]; in master_clk_init() 66 pll2_mult = 2; in arch_init_clk_ops() 68 pll2_mult = 4; in arch_init_clk_ops() 70 BUG_ON(!pll2_mult); in arch_init_clk_ops()`
/linux-6.3-rc2/drivers/clk/renesas/
A D	rcar-gen4-cpg.h	`57 u8 pll2_mult; member`
A D	rcar-gen4-cpg.c	`365 mult = cpg_pll_config->pll2_mult; in rcar_gen4_cpg_clk_register()`

Completed in 9 milliseconds