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Searched refs:pll_ctl_val (Results 1 – 1 of 1) sorted by relevance

/linux-6.3-rc2/arch/arm/mach-omap1/
A Dclock_data.c746 unsigned pll_ctl_val = omap_readw(DPLL_CTL); in omap1_clk_init() local
749 if (pll_ctl_val & 0x10) { in omap1_clk_init()
751 if (pll_ctl_val & 0xf80) in omap1_clk_init()
752 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; in omap1_clk_init()
753 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; in omap1_clk_init()
756 switch (pll_ctl_val & 0xc) { in omap1_clk_init()

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