| /linux-6.3-rc2/drivers/clk/actions/ |
| A D | owl-pll.c | 24 mul = pll_hw->min_mul; in owl_pll_calculate_mul()
26 mul = pll_hw->max_mul; in owl_pll_calculate_mul()
63 struct owl_pll_hw *pll_hw = &pll->pll_hw; in owl_pll_round_rate() local
67 if (pll_hw->table) { in owl_pll_round_rate()
74 return pll_hw->bfreq; in owl_pll_round_rate()
85 struct owl_pll_hw *pll_hw = &pll->pll_hw; in owl_pll_recalc_rate() local
89 if (pll_hw->table) { in owl_pll_recalc_rate()
100 return pll_hw->bfreq; in owl_pll_recalc_rate()
113 struct owl_pll_hw *pll_hw = &pll->pll_hw; in owl_pll_is_enabled() local
159 struct owl_pll_hw *pll_hw = &pll->pll_hw; in owl_pll_set_rate() local
[all …]
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| A D | owl-pll.h | 37 struct owl_pll_hw pll_hw; member
58 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
73 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
88 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
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| /linux-6.3-rc2/drivers/clk/microchip/ |
| A D | clk-mpfs-ccc.c | 202 struct mpfs_ccc_pll_hw_clock *pll_hw = &pll_hws[i]; in mpfs_ccc_register_plls() local
204 pll_hw->name = devm_kasprintf(dev, GFP_KERNEL, "ccc%s_pll%u", in mpfs_ccc_register_plls()
206 if (!pll_hw->name) in mpfs_ccc_register_plls()
209 pll_hw->base = data->pll_base[i]; in mpfs_ccc_register_plls()
210 pll_hw->hw.init = CLK_HW_INIT_PARENTS_DATA_FIXED_SIZE(pll_hw->name, in mpfs_ccc_register_plls()
211 pll_hw->parents, in mpfs_ccc_register_plls()
214 ret = devm_clk_hw_register(dev, &pll_hw->hw); in mpfs_ccc_register_plls()
217 pll_hw->id); in mpfs_ccc_register_plls()
219 data->hw_data.hws[pll_hw->id] = &pll_hw->hw; in mpfs_ccc_register_plls()
222 MPFS_CCC_OUTPUTS_PER_PLL, data, pll_hw); in mpfs_ccc_register_plls()
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| /linux-6.3-rc2/drivers/gpu/drm/msm/disp/mdp4/ |
| A D | mdp4_lvds_pll.c | 13 struct clk_hw pll_hw; member
17 #define to_mdp4_lvds_pll(x) container_of(x, struct mdp4_lvds_pll, pll_hw)
150 lvds_pll->pll_hw.init = &pll_init; in mpd4_lvds_pll_init()
151 clk = devm_clk_register(dev->dev, &lvds_pll->pll_hw); in mpd4_lvds_pll_init()
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| /linux-6.3-rc2/drivers/phy/mediatek/ |
| A D | phy-mtk-hdmi.c | 20 return container_of(hw, struct mtk_hdmi_phy, pll_hw); in to_mtk_hdmi_phy()
105 hdmi_phy->pll_hw.init = &clk_init; in mtk_hdmi_phy_probe()
106 hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw); in mtk_hdmi_phy_probe()
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| A D | phy-mtk-mipi-dsi.c | 10 return container_of(hw, struct mtk_mipi_tx, pll_hw); in mtk_mipi_tx_from_clk_hw()
160 mipi_tx->pll_hw.init = &clk_init; in mtk_mipi_tx_probe()
161 mipi_tx->pll = devm_clk_register(dev, &mipi_tx->pll_hw); in mtk_mipi_tx_probe()
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| A D | phy-mtk-hdmi.h | 34 struct clk_hw pll_hw; member
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| A D | phy-mtk-mipi-dsi.h | 34 struct clk_hw pll_hw; member
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| /linux-6.3-rc2/drivers/clk/ |
| A D | clk-asm9260.c | 258 struct clk_hw *hw, *pll_hw; in asm9260_acc_init() local
278 pll_hw = clk_hw_register_fixed_rate_parent_accuracy(NULL, pll_clk, &pll_parent_data, in asm9260_acc_init()
280 if (IS_ERR(pll_hw)) in asm9260_acc_init()
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| A D | clk-stm32f4.c | 745 struct clk_hw *pll_hw, spinlock_t *lock) in clk_register_pll_div() argument
772 pll_div->hw_pll = pll_hw; in clk_register_pll_div()
791 struct clk_hw *pll_hw; in stm32f4_rcc_register_pll() local
821 pll_hw = &pll->gate.hw; in stm32f4_rcc_register_pll()
822 ret = clk_hw_register(NULL, pll_hw); in stm32f4_rcc_register_pll()
838 pll_hw, in stm32f4_rcc_register_pll()
840 return pll_hw; in stm32f4_rcc_register_pll()
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| A D | clk-bm1880.c | 495 struct bm1880_pll_hw_clock *pll_hw = to_bm1880_pll_clk(hw); in bm1880_pll_recalc_rate() local
499 regval = readl(pll_hw->base + pll_hw->pll.reg); in bm1880_pll_recalc_rate()
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| /linux-6.3-rc2/drivers/gpu/drm/omapdrm/dss/ |
| A D | dsi.h | 332 const struct dss_pll_hw *pll_hw; member
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| A D | dsi.c | 4544 pll->hw = dsi->data->pll_hw; in dsi_init_pll_data()
4811 .pll_hw = &dss_omap3_dsi_pll_hw,
4823 .pll_hw = &dss_omap3_dsi_pll_hw,
4835 .pll_hw = &dss_omap4_dsi_pll_hw,
4849 .pll_hw = &dss_omap5_dsi_pll_hw,
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