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Searched refs:pll_settings (Results 1 – 10 of 10) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_clock_source.c193 struct pll_settings *pll_settings, in calc_fb_divider_checking_tolerance() argument
249 struct pll_settings *pll_settings, in calc_pll_dividers_in_range() argument
291 struct pll_settings *pll_settings) in calculate_pixel_clock_pll_dividers() argument
395 struct pll_settings *pll_settings) in pll_adjust_pix_clk() argument
473 struct pll_settings *pll_settings, in dce110_get_pix_clk_dividers_helper() argument
535 struct pll_settings *pll_settings, in dce112_get_pix_clk_dividers_helper() argument
567 struct pll_settings *pll_settings) in dce110_get_pix_clk_dividers() argument
600 struct pll_settings *pll_settings) in dce112_get_pix_clk_dividers() argument
844 struct pll_settings *pll_settings) in dce110_program_pix_clk() argument
918 struct pll_settings *pll_settings) in dce112_program_pix_clk() argument
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/inc/
A Dclock_source.h106 struct pll_settings { struct
167 struct pll_settings *);
171 struct pll_settings *);
A Dcore_types.h397 struct pll_settings pll_settings; member
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_hw_sequencer.c1351 pipe_ctx->pll_settings.feedback_divider; in build_audio_output()
1361 pipe_ctx->pll_settings.ss_percentage; in build_audio_output()
1432 &pipe_ctx->pll_settings)) { in dce110_enable_stream_timing()
3058 &pipes[i].pll_settings); in dce110_enable_dp_link_output()
A Ddce110_resource.c922 &pipe_ctx->pll_settings); in dce110_resource_build_pipe_hw_param()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_resource.c1052 &pipe_ctx->pll_settings); in build_pipe_hw_param()
A Ddcn10_hw_sequencer.c923 &pipe_ctx->pll_settings)) { in dcn10_enable_stream_timing()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn32/
A Ddcn32_hwseq.c1224 &pipe_ctx->pll_settings); in apply_symclk_on_tx_off_wa()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_resource.c1304 &pipe_ctx->pll_settings); in build_pipe_hw_param()
A Ddcn20_hwseq.c715 &pipe_ctx->pll_settings)) { in dcn20_enable_stream_timing()

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