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Searched refs:pmisc_addr (Results 1 – 10 of 10) sorted by relevance

/linux-6.3-rc2/drivers/crypto/qat/qat_common/
A Dadf_gen4_pfvf.c44 val = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_MSK) & ~vf_mask; in adf_gen4_enable_vf2pf_interrupts()
45 ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, val); in adf_gen4_enable_vf2pf_interrupts()
50 ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, ADF_GEN4_VF_MSK); in adf_gen4_disable_all_vf2pf_interrupts()
58 sources = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_SOU); in adf_gen4_disable_pending_vf2pf_interrupts()
63 disabled = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_MSK); in adf_gen4_disable_pending_vf2pf_interrupts()
77 ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, ADF_GEN4_VF_MSK); in adf_gen4_disable_pending_vf2pf_interrupts()
88 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_gen4_pfvf_send() local
98 ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val | ADF_PFVF_INT); in adf_gen4_pfvf_send()
104 true, pmisc_addr, pfvf_offset); in adf_gen4_pfvf_send()
115 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_gen4_pfvf_recv() local
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A Dadf_gen2_pfvf.c58 u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3) in adf_gen2_enable_vf2pf_interrupts()
60 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val); in adf_gen2_enable_vf2pf_interrupts()
67 u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3) in adf_gen2_disable_all_vf2pf_interrupts()
69 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val); in adf_gen2_disable_all_vf2pf_interrupts()
101 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3); in adf_gen2_disable_pending_vf2pf_interrupts()
104 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3); in adf_gen2_disable_pending_vf2pf_interrupts()
214 csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset); in adf_gen2_pfvf_send()
228 true, pmisc_addr, pfvf_offset); in adf_gen2_pfvf_send()
253 ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val); in adf_gen2_pfvf_send()
285 csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset); in adf_gen2_pfvf_recv()
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A Dadf_gen2_hw_data.c29 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_gen2_enable_error_correction() local
38 ADF_CSR_WR(pmisc_addr, ADF_GEN2_AE_CTX_ENABLES(i), val); in adf_gen2_enable_error_correction()
46 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_UERRSSMSH(i)); in adf_gen2_enable_error_correction()
48 ADF_CSR_WR(pmisc_addr, ADF_GEN2_UERRSSMSH(i), val); in adf_gen2_enable_error_correction()
49 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_CERRSSMSH(i)); in adf_gen2_enable_error_correction()
51 ADF_CSR_WR(pmisc_addr, ADF_GEN2_CERRSSMSH(i), val); in adf_gen2_enable_error_correction()
65 reg = READ_CSR_AE2FUNCTION_MAP_A(pmisc_addr, i); in adf_gen2_cfg_iov_thds()
70 WRITE_CSR_AE2FUNCTION_MAP_A(pmisc_addr, i, reg); in adf_gen2_cfg_iov_thds()
75 reg = READ_CSR_AE2FUNCTION_MAP_B(pmisc_addr, i); in adf_gen2_cfg_iov_thds()
80 WRITE_CSR_AE2FUNCTION_MAP_B(pmisc_addr, i, reg); in adf_gen2_cfg_iov_thds()
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A Dadf_gen4_hw_data.c114 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_gen4_set_ssm_wdtimer() local
130 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTL_OFFSET, ssm_wdt_low); in adf_gen4_set_ssm_wdtimer()
131 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTH_OFFSET, ssm_wdt_high); in adf_gen4_set_ssm_wdtimer()
133 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKEL_OFFSET, ssm_wdt_pke_low); in adf_gen4_set_ssm_wdtimer()
134 ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKEH_OFFSET, ssm_wdt_pke_high); in adf_gen4_set_ssm_wdtimer()
A Dadf_isr.c61 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_enable_vf2pf_interrupts() local
65 GET_PFVF_OPS(accel_dev)->enable_vf2pf_interrupts(pmisc_addr, vf_mask); in adf_enable_vf2pf_interrupts()
71 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_disable_all_vf2pf_interrupts() local
75 GET_PFVF_OPS(accel_dev)->disable_all_vf2pf_interrupts(pmisc_addr); in adf_disable_all_vf2pf_interrupts()
81 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_disable_pending_vf2pf_interrupts() local
85 pending = GET_PFVF_OPS(accel_dev)->disable_pending_vf2pf_interrupts(pmisc_addr); in adf_disable_pending_vf2pf_interrupts()
A Dadf_vf_isr.c33 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_enable_pf2vf_interrupts() local
35 ADF_CSR_WR(pmisc_addr, ADF_VINTMSK_OFFSET, 0x0); in adf_enable_pf2vf_interrupts()
40 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_disable_pf2vf_interrupts() local
42 ADF_CSR_WR(pmisc_addr, ADF_VINTMSK_OFFSET, 0x2); in adf_disable_pf2vf_interrupts()
A Dadf_admin.c295 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in adf_init_admin_comms() local
329 mailbox = pmisc_addr + mailbox_offset; in adf_init_admin_comms()
334 ADF_CSR_WR(pmisc_addr, adminmsg_u, upper_32_bits(reg_val)); in adf_init_admin_comms()
335 ADF_CSR_WR(pmisc_addr, adminmsg_l, lower_32_bits(reg_val)); in adf_init_admin_comms()
A Dadf_accel_devices.h157 void (*enable_vf2pf_interrupts)(void __iomem *pmisc_addr, u32 vf_mask);
158 void (*disable_all_vf2pf_interrupts)(void __iomem *pmisc_addr);
159 u32 (*disable_pending_vf2pf_interrupts)(void __iomem *pmisc_addr);
A Dqat_hal.c687 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); in qat_hal_chip_init() local
718 handle->hal_cap_g_ctl_csr_addr_v = pmisc_addr + ICP_QAT_CAP_OFFSET_4XXX; in qat_hal_chip_init()
719 handle->hal_cap_ae_xfer_csr_addr_v = pmisc_addr + ICP_QAT_AE_OFFSET_4XXX; in qat_hal_chip_init()
720 handle->hal_ep_csr_addr_v = pmisc_addr + ICP_QAT_EP_OFFSET_4XXX; in qat_hal_chip_init()
746 handle->hal_cap_g_ctl_csr_addr_v = pmisc_addr + ICP_QAT_CAP_OFFSET; in qat_hal_chip_init()
747 handle->hal_cap_ae_xfer_csr_addr_v = pmisc_addr + ICP_QAT_AE_OFFSET; in qat_hal_chip_init()
748 handle->hal_ep_csr_addr_v = pmisc_addr + ICP_QAT_EP_OFFSET; in qat_hal_chip_init()
773 handle->hal_cap_g_ctl_csr_addr_v = pmisc_addr + ICP_QAT_CAP_OFFSET; in qat_hal_chip_init()
774 handle->hal_cap_ae_xfer_csr_addr_v = pmisc_addr + ICP_QAT_AE_OFFSET; in qat_hal_chip_init()
775 handle->hal_ep_csr_addr_v = pmisc_addr + ICP_QAT_EP_OFFSET; in qat_hal_chip_init()
/linux-6.3-rc2/drivers/crypto/qat/qat_dh895xcc/
A Dadf_dh895xcc_hw_data.c118 u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3) in enable_vf2pf_interrupts()
120 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val); in enable_vf2pf_interrupts()
125 u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK5) in enable_vf2pf_interrupts()
127 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, val); in enable_vf2pf_interrupts()
136 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3) in disable_all_vf2pf_interrupts()
138 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val); in disable_all_vf2pf_interrupts()
141 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK5) in disable_all_vf2pf_interrupts()
143 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, val); in disable_all_vf2pf_interrupts()
182 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3); in disable_pending_vf2pf_interrupts()
183 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, errmsk5); in disable_pending_vf2pf_interrupts()
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