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Searched refs:postdiv (Results 1 – 25 of 29) sorted by relevance

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/linux-6.3-rc2/arch/mips/ath79/
A Dclock.c315 cpu_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
317 cpu_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
325 ddr_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
327 ddr_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
335 ahb_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
337 ahb_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
404 cpu_rate = cpu_pll / (postdiv + 1); in qca953x_clocks_init()
406 cpu_rate = ddr_pll / (postdiv + 1); in qca953x_clocks_init()
414 ddr_rate = ddr_pll / (postdiv + 1); in qca953x_clocks_init()
416 ddr_rate = cpu_pll / (postdiv + 1); in qca953x_clocks_init()
[all …]
/linux-6.3-rc2/arch/mips/ar7/
A Dclock.c74 u32 postdiv; member
101 int *postdiv, int *mul) in approximate() argument
112 *postdiv = k; in approximate()
126 *postdiv = tmp_base / tmp_gcd; in calculate()
129 if ((*postdiv > 0) & (*postdiv <= 32)) in calculate()
135 tmp_freq = base / *prediv * *mul / *postdiv; in calculate()
142 *prediv, *postdiv, *mul); in calculate()
169 int postdiv = (ctrl & POSTDIV_MASK) + 1; in tnetd7300_get_clock() local
170 int divisor = prediv * postdiv; in tnetd7300_get_clock()
210 int prediv, postdiv, mul; in tnetd7300_set_clock() local
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/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-pll.c41 u32 pcw, int postdiv) in __mtk_pll_recalc_rate() argument
64 return ((unsigned long)vco + postdiv - 1) / postdiv; in __mtk_pll_recalc_rate()
94 int postdiv) in mtk_pll_set_rate_regs() argument
157 *postdiv = 1 << val; in mtk_pll_calc_values()
160 *postdiv = 1 << val; in mtk_pll_calc_values()
161 if ((u64)freq * *postdiv >= fmin) in mtk_pll_calc_values()
179 u32 postdiv; in mtk_pll_set_rate() local
182 mtk_pll_set_rate_regs(pll, pcw, postdiv); in mtk_pll_set_rate()
190 u32 postdiv; in mtk_pll_recalc_rate() local
194 postdiv = 1 << postdiv; in mtk_pll_recalc_rate()
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A Dclk-fhctl.c151 static void __set_postdiv(struct mtk_clk_pll *pll, unsigned int postdiv) in __set_postdiv() argument
157 regval |= (ffs(postdiv) - 1) << pll->data->pd_shift; in __set_postdiv()
162 unsigned int postdiv) in fhctl_hopping() argument
173 if (postdiv) { in fhctl_hopping()
176 if (postdiv > pll_postdiv) in fhctl_hopping()
177 __set_postdiv(pll, postdiv); in fhctl_hopping()
186 if (postdiv && postdiv < pll_postdiv) in fhctl_hopping()
187 __set_postdiv(pll, postdiv); in fhctl_hopping()
A Dclk-pllfh.c33 u32 postdiv; in mtk_fhctl_set_rate() local
35 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); in mtk_fhctl_set_rate()
37 return fh->ops->hopping(fh, pcw, postdiv); in mtk_fhctl_set_rate()
A Dclk-pllfh.h66 unsigned int postdiv);
A Dclk-pll.h94 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
/linux-6.3-rc2/drivers/clk/mmp/
A Dclk-audio.c119 unsigned int postdiv; in audio_pll_recalc_rate() local
138 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) { in audio_pll_recalc_rate()
144 val |= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(postdivs[postdiv].modulo); in audio_pll_recalc_rate()
157 freq /= postdivs[postdiv].divisor; in audio_pll_recalc_rate()
169 unsigned int postdiv; in audio_pll_round_rate() local
175 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) { in audio_pll_round_rate()
178 freq /= postdivs[postdiv].divisor; in audio_pll_round_rate()
197 unsigned int postdiv; in audio_pll_set_rate() local
204 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) { in audio_pll_set_rate()
205 if (rate * postdivs[postdiv].divisor != predivs[prediv].freq_vco) in audio_pll_set_rate()
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A Dclk-pll.c49 u32 fbdiv, refdiv, postdiv; in mmp_clk_pll_recalc_rate() local
71 postdiv = (val >> pll->postdiv_shift) & 0x7; in mmp_clk_pll_recalc_rate()
76 do_div(rate, postdivs[postdiv]); in mmp_clk_pll_recalc_rate()
/linux-6.3-rc2/drivers/clk/keystone/
A Dpll.c60 u32 postdiv; member
81 u32 mult = 0, prediv, postdiv, val; in clk_pllclk_recalc() local
100 postdiv = ((val & pll_data->clkod_mask) >> in clk_pllclk_recalc()
103 postdiv = readl(pll_data->pllod); in clk_pllclk_recalc()
104 postdiv = ((postdiv & pll_data->clkod_mask) >> in clk_pllclk_recalc()
107 postdiv = pll_data->postdiv; in clk_pllclk_recalc()
111 rate /= postdiv; in clk_pllclk_recalc()
172 if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv)) { in _of_pll_clk_init()
/linux-6.3-rc2/drivers/media/i2c/
A Dtc358746.c818 u8 postdiv; in tc358746_find_pll_settings() local
826 postdiv = 1; in tc358746_find_pll_settings()
828 postdiv = 2; in tc358746_find_pll_settings()
830 postdiv = 4; in tc358746_find_pll_settings()
832 postdiv = 8; in tc358746_find_pll_settings()
1136 if (postdiv % 2) in tc358746_find_mclk_settings()
1139 if (postdiv >= 4 && postdiv <= 512) { in tc358746_find_mclk_settings()
1141 mclk_postdiv = postdiv; in tc358746_find_mclk_settings()
1148 for (postdiv = 4; postdiv <= 512; postdiv += 2) { in tc358746_find_mclk_settings()
1151 pre = mclkdiv / postdiv; in tc358746_find_mclk_settings()
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A Dov2659.c897 u32 prediv, postdiv, mult; in ov2659_pll_calc_params() local
903 postdiv = ctrl1[i].div; in ov2659_pll_calc_params()
910 actual /= postdiv; in ov2659_pll_calc_params()
/linux-6.3-rc2/drivers/clk/microchip/
A Dclk-mpfs.c102 u32 mult, ref_div, postdiv; in mpfs_clk_msspll_recalc_rate() local
108 postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; in mpfs_clk_msspll_recalc_rate()
109 postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); in mpfs_clk_msspll_recalc_rate()
111 return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); in mpfs_clk_msspll_recalc_rate()
139 u32 mult, ref_div, postdiv; in mpfs_clk_msspll_set_rate() local
157 postdiv = readl_relaxed(postdiv_addr); in mpfs_clk_msspll_set_rate()
158 postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); in mpfs_clk_msspll_set_rate()
159 writel_relaxed(postdiv, postdiv_addr); in mpfs_clk_msspll_set_rate()
/linux-6.3-rc2/drivers/gpu/drm/msm/dsi/phy/
A Ddsi_phy_14nm.c603 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_recalc_rate()
605 u8 shift = postdiv->shift; in dsi_pll_14nm_postdiv_recalc_rate()
606 u8 width = postdiv->width; in dsi_pll_14nm_postdiv_recalc_rate()
615 postdiv->flags, width); in dsi_pll_14nm_postdiv_recalc_rate()
623 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_round_rate()
628 postdiv->width, in dsi_pll_14nm_postdiv_round_rate()
629 postdiv->flags); in dsi_pll_14nm_postdiv_round_rate()
636 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_set_rate()
639 u8 shift = postdiv->shift; in dsi_pll_14nm_postdiv_set_rate()
640 u8 width = postdiv->width; in dsi_pll_14nm_postdiv_set_rate()
[all …]
/linux-6.3-rc2/drivers/clk/
A Dclk-tps68470.c35 unsigned int postdiv; member
171 regmap_write(clkdata->regmap, TPS68470_REG_POSTDIV, clk_freqs[idx].postdiv); in tps68470_clk_set_rate()
172 regmap_write(clkdata->regmap, TPS68470_REG_POSTDIV2, clk_freqs[idx].postdiv); in tps68470_clk_set_rate()
A Dclk-axm5516.c52 unsigned long rate, fbdiv, refdiv, postdiv; in axxia_pllclk_recalc() local
56 postdiv = ((control >> 0) & 0xf) + 1; in axxia_pllclk_recalc()
59 rate = (parent_rate / (refdiv * postdiv)) * fbdiv; in axxia_pllclk_recalc()
/linux-6.3-rc2/Documentation/devicetree/bindings/clock/
A Dkeystone-pll.txt20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
21 for postdiv
30 fixed-postdiv = <2>;
/linux-6.3-rc2/drivers/gpu/drm/bridge/
A Dlontium-lt9611.c172 … lt9611_pcr_setup(struct lt9611 *lt9611, const struct drm_display_mode *mode, unsigned int postdiv) in lt9611_pcr_setup() argument
174 unsigned int pcr_m = mode->clock * 5 * postdiv / 27000; in lt9611_pcr_setup()
222 …lt9611_pll_setup(struct lt9611 *lt9611, const struct drm_display_mode *mode, unsigned int *postdiv) in lt9611_pll_setup() argument
243 *postdiv = 1; in lt9611_pll_setup()
246 *postdiv = 2; in lt9611_pll_setup()
249 *postdiv = 4; in lt9611_pll_setup()
694 unsigned int postdiv; in lt9611_bridge_atomic_enable() local
711 lt9611_pll_setup(lt9611, mode, &postdiv); in lt9611_bridge_atomic_enable()
713 lt9611_pcr_setup(lt9611, mode, postdiv); in lt9611_bridge_atomic_enable()
/linux-6.3-rc2/drivers/clk/visconti/
A Dpll.c59 u32 postdiv, val; in visconti_pll_get_params() local
70 postdiv = readl(pll->pll_base + PLL_POSTDIV_REG); in visconti_pll_get_params()
71 rate_table->postdiv1 = postdiv & PLL_POSTDIV_MASK; in visconti_pll_get_params()
72 rate_table->postdiv2 = (postdiv >> 4) & PLL_POSTDIV_MASK; in visconti_pll_get_params()
/linux-6.3-rc2/drivers/clk/imx/
A Dclk-composite-8m.c52 int *prediv, int *postdiv) in imx8m_clk_composite_compute_dividers() argument
59 *postdiv = 1; in imx8m_clk_composite_compute_dividers()
67 *postdiv = div2; in imx8m_clk_composite_compute_dividers()
/linux-6.3-rc2/drivers/video/fbdev/
A Dgxt4500.c239 int m, n, pdiv1, pdiv2, postdiv; in calc_pll() local
249 postdiv = pdiv1 * pdiv2; in calc_pll()
250 pll_period = DIV_ROUND_UP(period_ps, postdiv); in calc_pll()
258 n = intf * postdiv / period_ps; in calc_pll()
261 t = par->refclk_ps * m * postdiv / n; in calc_pll()
/linux-6.3-rc2/drivers/phy/rockchip/
A Dphy-rockchip-inno-hdmi.c270 u8 postdiv; member
917 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3228_power_on()
921 int div = cfg->postdiv / 2 - 1; in inno_hdmi_phy_rk3228_power_on()
1023 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3328_power_on()
1028 v = (cfg->postdiv / 2) - 1; in inno_hdmi_phy_rk3328_power_on()
/linux-6.3-rc2/drivers/gpu/drm/amd/pm/powerplay/smumgr/
A Dvegam_smumgr.c684 table->SclkFcwRangeTable[i].postdiv = in vegam_get_sclk_range_table()
703 (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv; in vegam_get_sclk_range_table()
705 (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv; in vegam_get_sclk_range_table()
708 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv; in vegam_get_sclk_range_table()
761 ((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
763 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in vegam_calculate_sclk_params()
771 ((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
780 ((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
782 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in vegam_calculate_sclk_params()
A Dpolaris10_smumgr.c860 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv; in polaris10_get_sclk_range_table()
874 …le[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv; in polaris10_get_sclk_range_table()
875 …le[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv; in polaris10_get_sclk_range_table()
878 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv; in polaris10_get_sclk_range_table()
930 …_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
931 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in polaris10_calculate_sclk_params()
938 …nt16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
945 …int16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
946 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in polaris10_calculate_sclk_params()
/linux-6.3-rc2/drivers/clk/rockchip/
A Dclk-pll.c900 u64 rate64 = prate, postdiv; in rockchip_rk3588_pll_recalc_rate() local
911 postdiv = cur.p * 65535; in rockchip_rk3588_pll_recalc_rate()
912 do_div(frac_rate64, postdiv); in rockchip_rk3588_pll_recalc_rate()

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