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Searched refs:postdiv2 (Results 1 – 9 of 9) sorted by relevance

/linux-6.3-rc2/drivers/clk/pistachio/
A Dclk-pll.c241 params->postdiv2 != old_postdiv2)) in pll_gf40lp_frac_set_rate()
244 if (params->postdiv2 > params->postdiv1) in pll_gf40lp_frac_set_rate()
254 (params->postdiv2 << PLL_FRAC_CTRL2_POSTDIV2_SHIFT); in pll_gf40lp_frac_set_rate()
273 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; in pll_gf40lp_frac_recalc_rate() local
282 postdiv2 = (val >> PLL_FRAC_CTRL2_POSTDIV2_SHIFT) & in pll_gf40lp_frac_recalc_rate()
387 params->postdiv2 != old_postdiv2)) in pll_gf40lp_laint_set_rate()
390 if (params->postdiv2 > params->postdiv1) in pll_gf40lp_laint_set_rate()
400 (params->postdiv2 << PLL_INT_CTRL1_POSTDIV2_SHIFT); in pll_gf40lp_laint_set_rate()
413 u32 val, prediv, fbdiv, postdiv1, postdiv2; in pll_gf40lp_laint_recalc_rate() local
421 postdiv2 = (val >> PLL_INT_CTRL1_POSTDIV2_SHIFT) & in pll_gf40lp_laint_recalc_rate()
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A Dclk.h100 unsigned long long postdiv2; member
/linux-6.3-rc2/drivers/clk/rockchip/
A Dclk-pll.c153 rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT) in rockchip_rk3036_pll_get_params()
184 do_div(rate64, cur.postdiv2); in rockchip_rk3036_pll_recalc_rate()
202 rate->postdiv2, rate->dsmpd, rate->frac); in rockchip_rk3036_pll_set_params()
318 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, in rockchip_rk3036_pll_init()
321 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3036_pll_init()
325 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || in rockchip_rk3036_pll_init()
633 rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT) in rockchip_rk3399_pll_get_params()
666 do_div(rate64, cur.postdiv2); in rockchip_rk3399_pll_recalc_rate()
684 rate->postdiv2, rate->dsmpd, rate->frac); in rockchip_rk3399_pll_set_params()
802 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, in rockchip_rk3399_pll_init()
[all …]
A Dclk.h299 .postdiv2 = _postdiv2, \
362 unsigned int postdiv2; member
/linux-6.3-rc2/drivers/clk/visconti/
A Dpll.h33 .postdiv2 = _postdiv2 \
44 unsigned int postdiv2; member
A Dpll.c49 #define PLL_CREATE_OSTDIV(table) (table->postdiv2 << 4 | table->postdiv1)
72 rate_table->postdiv2 = (postdiv >> 4) & PLL_POSTDIV_MASK; in visconti_pll_get_params()
/linux-6.3-rc2/arch/mips/ar7/
A Dclock.c75 u32 postdiv2; member
272 int prediv, int postdiv, int postdiv2, int mul, u32 frequency) in tnetd7200_set_clock() argument
277 base, frequency, prediv, postdiv, postdiv2, mul); in tnetd7200_set_clock()
294 writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2); in tnetd7200_set_clock()
/linux-6.3-rc2/drivers/gpu/drm/msm/dsi/phy/
A Ddsi_phy_28nm_8960.c51 u8 postdiv2; member
351 cached_state->postdiv2 = in dsi_28nm_pll_save_state()
377 cached_state->postdiv2); in dsi_28nm_pll_restore_state()
/linux-6.3-rc2/drivers/clk/
A Dclk-bm1880.c478 u32 postdiv1, postdiv2, denominator; in bm1880_pll_rate_calc() local
483 postdiv2 = (regval >> 12) & 0x7; in bm1880_pll_rate_calc()
486 denominator = refdiv * postdiv1 * postdiv2; in bm1880_pll_rate_calc()

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