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Searched refs:radeon_ring_write (Results 1 – 22 of 22) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/radeon/
A Duvd_v2_2.c45 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); in uvd_v2_2_fence_emit()
46 radeon_ring_write(ring, fence->seq); in uvd_v2_2_fence_emit()
48 radeon_ring_write(ring, lower_32_bits(addr)); in uvd_v2_2_fence_emit()
50 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); in uvd_v2_2_fence_emit()
52 radeon_ring_write(ring, 0); in uvd_v2_2_fence_emit()
55 radeon_ring_write(ring, 0); in uvd_v2_2_fence_emit()
57 radeon_ring_write(ring, 0); in uvd_v2_2_fence_emit()
59 radeon_ring_write(ring, 2); in uvd_v2_2_fence_emit()
80 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF); in uvd_v2_2_semaphore_emit()
85 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); in uvd_v2_2_semaphore_emit()
[all …]
A Devergreen_dma.c46 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0)); in evergreen_dma_fence_ring_emit()
47 radeon_ring_write(ring, addr & 0xfffffffc); in evergreen_dma_fence_ring_emit()
48 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in evergreen_dma_fence_ring_emit()
49 radeon_ring_write(ring, fence->seq); in evergreen_dma_fence_ring_emit()
51 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0)); in evergreen_dma_fence_ring_emit()
55 radeon_ring_write(ring, 1); in evergreen_dma_fence_ring_emit()
79 radeon_ring_write(ring, next_rptr); in evergreen_dma_ring_ib_execute()
86 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0)); in evergreen_dma_ring_ib_execute()
88 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in evergreen_dma_ring_ib_execute()
140 radeon_ring_write(ring, dst_offset & 0xfffffffc); in evergreen_copy_dma()
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A Dcik_sdma.c147 radeon_ring_write(ring, next_rptr); in cik_sdma_ring_ib_execute()
156 radeon_ring_write(ring, ib->length_dw); in cik_sdma_ring_ib_execute()
209 radeon_ring_write(ring, fence->seq); in cik_sdma_fence_ring_emit()
672 radeon_ring_write(ring, 0xDEADBEEF); in cik_sdma_ring_test()
965 radeon_ring_write(ring, 0); in cik_dma_vm_flush()
969 radeon_ring_write(ring, 0); in cik_dma_vm_flush()
973 radeon_ring_write(ring, 1); in cik_dma_vm_flush()
977 radeon_ring_write(ring, 0); in cik_dma_vm_flush()
981 radeon_ring_write(ring, VMID(0)); in cik_dma_vm_flush()
989 radeon_ring_write(ring, 1 << vm_id); in cik_dma_vm_flush()
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A Duvd_v1_0.c92 radeon_ring_write(ring, 0); in uvd_v1_0_fence_emit()
95 radeon_ring_write(ring, 0); in uvd_v1_0_fence_emit()
97 radeon_ring_write(ring, 0); in uvd_v1_0_fence_emit()
99 radeon_ring_write(ring, 2); in uvd_v1_0_fence_emit()
187 radeon_ring_write(ring, tmp); in uvd_v1_0_init()
188 radeon_ring_write(ring, 0xFFFFF); in uvd_v1_0_init()
191 radeon_ring_write(ring, tmp); in uvd_v1_0_init()
192 radeon_ring_write(ring, 0xFFFFF); in uvd_v1_0_init()
195 radeon_ring_write(ring, tmp); in uvd_v1_0_init()
200 radeon_ring_write(ring, 0x8); in uvd_v1_0_init()
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A Dsi_dma.c196 radeon_ring_write(ring, pd_addr >> 12); in si_dma_vm_flush()
201 radeon_ring_write(ring, 1); in si_dma_vm_flush()
206 radeon_ring_write(ring, 1 << vm_id); in si_dma_vm_flush()
210 radeon_ring_write(ring, VM_INVALIDATE_REQUEST); in si_dma_vm_flush()
211 radeon_ring_write(ring, 0xff << 16); /* retry */ in si_dma_vm_flush()
212 radeon_ring_write(ring, 1 << vm_id); /* mask */ in si_dma_vm_flush()
213 radeon_ring_write(ring, 0); /* value */ in si_dma_vm_flush()
263 radeon_ring_write(ring, lower_32_bits(dst_offset)); in si_copy_dma()
264 radeon_ring_write(ring, lower_32_bits(src_offset)); in si_copy_dma()
265 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in si_copy_dma()
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A Dr600_dma.c254 radeon_ring_write(ring, lower_32_bits(gpu_addr)); in r600_dma_ring_test()
256 radeon_ring_write(ring, 0xDEADBEEF); in r600_dma_ring_test()
294 radeon_ring_write(ring, addr & 0xfffffffc); in r600_dma_fence_ring_emit()
295 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in r600_dma_fence_ring_emit()
296 radeon_ring_write(ring, lower_32_bits(fence->seq)); in r600_dma_fence_ring_emit()
321 radeon_ring_write(ring, addr & 0xfffffffc); in r600_dma_semaphore_ring_emit()
322 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); in r600_dma_semaphore_ring_emit()
416 radeon_ring_write(ring, next_rptr); in r600_dma_ring_ib_execute()
425 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in r600_dma_ring_ib_execute()
476 radeon_ring_write(ring, dst_offset & 0xfffffffc); in r600_copy_dma()
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A Dni_dma.c132 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); in cayman_dma_ring_ib_execute()
133 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in cayman_dma_ring_ib_execute()
135 radeon_ring_write(ring, next_rptr); in cayman_dma_ring_ib_execute()
142 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); in cayman_dma_ring_ib_execute()
144 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in cayman_dma_ring_ib_execute()
453 radeon_ring_write(ring, pd_addr >> 12); in cayman_dma_vm_flush()
458 radeon_ring_write(ring, 1); in cayman_dma_vm_flush()
463 radeon_ring_write(ring, 1 << vm_id); in cayman_dma_vm_flush()
466 radeon_ring_write(ring, DMA_SRBM_READ_PACKET); in cayman_dma_vm_flush()
468 radeon_ring_write(ring, 0); /* mask */ in cayman_dma_vm_flush()
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A Duvd_v3_1.c46 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); in uvd_v3_1_semaphore_emit()
47 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF); in uvd_v3_1_semaphore_emit()
49 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); in uvd_v3_1_semaphore_emit()
50 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF); in uvd_v3_1_semaphore_emit()
52 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); in uvd_v3_1_semaphore_emit()
53 radeon_ring_write(ring, 0x80 | (emit_wait ? 1 : 0)); in uvd_v3_1_semaphore_emit()
A Dr300.c220 radeon_ring_write(ring, 0); in r300_fence_ring_emit()
222 radeon_ring_write(ring, 0); in r300_fence_ring_emit()
273 radeon_ring_write(ring, in r300_ring_start()
281 radeon_ring_write(ring, in r300_ring_start()
287 radeon_ring_write(ring, 0); in r300_ring_start()
289 radeon_ring_write(ring, 0); in r300_ring_start()
295 radeon_ring_write(ring, in r300_ring_start()
305 radeon_ring_write(ring, in r300_ring_start()
315 radeon_ring_write(ring, in r300_ring_start()
326 radeon_ring_write(ring, in r300_ring_start()
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A Dni.c1401 radeon_ring_write(ring, 0); in cayman_fence_ring_emit()
1409 radeon_ring_write(ring, 0); in cayman_fence_ring_emit()
1421 radeon_ring_write(ring, 1); in cayman_ring_ib_execute()
1432 radeon_ring_write(ring, in cayman_ring_ib_execute()
1444 radeon_ring_write(ring, 0); in cayman_ring_ib_execute()
1548 radeon_ring_write(ring, 0x1); in cayman_cp_start()
1549 radeon_ring_write(ring, 0x0); in cayman_cp_start()
1552 radeon_ring_write(ring, 0); in cayman_cp_start()
1553 radeon_ring_write(ring, 0); in cayman_cp_start()
1576 radeon_ring_write(ring, 0); in cayman_cp_start()
[all …]
A Drv515.c60 radeon_ring_write(ring, in rv515_ring_start()
70 radeon_ring_write(ring, 0); in rv515_ring_start()
72 radeon_ring_write(ring, 0); in rv515_ring_start()
76 radeon_ring_write(ring, 0); in rv515_ring_start()
80 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); in rv515_ring_start()
84 radeon_ring_write(ring, 0); in rv515_ring_start()
88 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); in rv515_ring_start()
90 radeon_ring_write(ring, in rv515_ring_start()
100 radeon_ring_write(ring, in rv515_ring_start()
114 radeon_ring_write(ring, PACKET0(0x20C8, 0)); in rv515_ring_start()
[all …]
A Drv770_dma.c74 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); in rv770_copy_dma()
75 radeon_ring_write(ring, dst_offset & 0xfffffffc); in rv770_copy_dma()
76 radeon_ring_write(ring, src_offset & 0xfffffffc); in rv770_copy_dma()
77 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in rv770_copy_dma()
78 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in rv770_copy_dma()
A Dradeon_vce.c701 radeon_ring_write(ring, cpu_to_le32(VCE_CMD_SEMAPHORE)); in radeon_vce_semaphore_emit()
706 radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END)); in radeon_vce_semaphore_emit()
721 radeon_ring_write(ring, cpu_to_le32(VCE_CMD_IB)); in radeon_vce_ib_execute()
722 radeon_ring_write(ring, cpu_to_le32(ib->gpu_addr)); in radeon_vce_ib_execute()
724 radeon_ring_write(ring, cpu_to_le32(ib->length_dw)); in radeon_vce_ib_execute()
740 radeon_ring_write(ring, cpu_to_le32(VCE_CMD_FENCE)); in radeon_vce_fence_emit()
741 radeon_ring_write(ring, cpu_to_le32(addr)); in radeon_vce_fence_emit()
743 radeon_ring_write(ring, cpu_to_le32(fence->seq)); in radeon_vce_fence_emit()
744 radeon_ring_write(ring, cpu_to_le32(VCE_CMD_TRAP)); in radeon_vce_fence_emit()
745 radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END)); in radeon_vce_fence_emit()
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A Dr600.c2698 radeon_ring_write(ring, 0x1); in r600_cp_start()
2700 radeon_ring_write(ring, 0x0); in r600_cp_start()
2703 radeon_ring_write(ring, 0x3); in r600_cp_start()
2707 radeon_ring_write(ring, 0); in r600_cp_start()
2708 radeon_ring_write(ring, 0); in r600_cp_start()
2883 radeon_ring_write(ring, 0); in r600_fence_ring_emit()
2891 radeon_ring_write(ring, 0); in r600_fence_ring_emit()
2897 radeon_ring_write(ring, 0); in r600_fence_ring_emit()
2945 radeon_ring_write(ring, 0x0); in r600_semaphore_ring_emit()
3383 radeon_ring_write(ring, 0); in r600_ring_ib_execute()
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A Dcik.c3558 radeon_ring_write(ring, 0); in cik_fence_gfx_ring_emit()
3569 radeon_ring_write(ring, 0); in cik_fence_gfx_ring_emit()
3597 radeon_ring_write(ring, 0); in cik_fence_compute_ring_emit()
4011 radeon_ring_write(ring, 0); in cik_cp_gfx_start()
5686 radeon_ring_write(ring, in cik_vm_flush()
5689 radeon_ring_write(ring, in cik_vm_flush()
5692 radeon_ring_write(ring, 0); in cik_vm_flush()
5700 radeon_ring_write(ring, 0); in cik_vm_flush()
5707 radeon_ring_write(ring, 0); in cik_vm_flush()
5718 radeon_ring_write(ring, 0); in cik_vm_flush()
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A Dsi.c3378 radeon_ring_write(ring, 0); in si_fence_ring_emit()
3385 radeon_ring_write(ring, 0); in si_fence_ring_emit()
3393 radeon_ring_write(ring, 0); in si_fence_ring_emit()
3432 radeon_ring_write(ring, in si_ring_ib_execute()
3572 radeon_ring_write(ring, 0); in si_cp_start()
3573 radeon_ring_write(ring, 0); in si_cp_start()
3602 radeon_ring_write(ring, 0); in si_cp_start()
5080 radeon_ring_write(ring, in si_vm_flush()
5083 radeon_ring_write(ring, in si_vm_flush()
5086 radeon_ring_write(ring, 0); in si_vm_flush()
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A Dr200.c105 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r200_copy_dma()
106 radeon_ring_write(ring, (1 << 16)); in r200_copy_dma()
113 radeon_ring_write(ring, PACKET0(0x720, 2)); in r200_copy_dma()
114 radeon_ring_write(ring, src_offset); in r200_copy_dma()
115 radeon_ring_write(ring, dst_offset); in r200_copy_dma()
116 radeon_ring_write(ring, cur_size | (1 << 31) | (1 << 30)); in r200_copy_dma()
120 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r200_copy_dma()
121 radeon_ring_write(ring, RADEON_WAIT_DMA_GUI_IDLE); in r200_copy_dma()
A Dr420.c220 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); in r420_cp_errata_init()
221 radeon_ring_write(ring, rdev->config.r300.resync_scratch); in r420_cp_errata_init()
222 radeon_ring_write(ring, 0xDEADBEEF); in r420_cp_errata_init()
236 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); in r420_cp_errata_fini()
237 radeon_ring_write(ring, R300_RB3D_DC_FINISH); in r420_cp_errata_fini()
A Dr100.c885 radeon_ring_write(ring, fence->seq); in r100_fence_ring_emit()
940 radeon_ring_write(ring, in r100_copy_blit()
955 radeon_ring_write(ring, 0); in r100_copy_blit()
957 radeon_ring_write(ring, num_gpu_pages); in r100_copy_blit()
958 radeon_ring_write(ring, num_gpu_pages); in r100_copy_blit()
964 radeon_ring_write(ring, in r100_copy_blit()
1001 radeon_ring_write(ring, in r100_ring_start()
3668 radeon_ring_write(ring, 0xDEADBEEF); in r100_ring_test()
3695 radeon_ring_write(ring, next_rptr); in r100_ring_ib_execute()
3699 radeon_ring_write(ring, ib->gpu_addr); in r100_ring_ib_execute()
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A Devergreen.c2939 radeon_ring_write(ring, 1); in evergreen_ring_ib_execute()
2946 radeon_ring_write(ring, next_rptr); in evergreen_ring_ib_execute()
2952 radeon_ring_write(ring, next_rptr); in evergreen_ring_ib_execute()
2953 radeon_ring_write(ring, 0); in evergreen_ring_ib_execute()
2957 radeon_ring_write(ring, in evergreen_ring_ib_execute()
3011 radeon_ring_write(ring, 0x1); in evergreen_cp_start()
3012 radeon_ring_write(ring, 0x0); in evergreen_cp_start()
3015 radeon_ring_write(ring, 0); in evergreen_cp_start()
3016 radeon_ring_write(ring, 0); in evergreen_cp_start()
3040 radeon_ring_write(ring, 0); in evergreen_cp_start()
[all …]
A Dradeon_ring.c177 radeon_ring_write(ring, ring->nop); in radeon_ring_commit()
361 radeon_ring_write(ring, data[i]); in radeon_ring_restore()
A Dradeon.h2718 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) in radeon_ring_write() function

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