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/linux-6.3-rc2/drivers/clk/mvebu/
A Dclk-corediv.c44 u32 ratio_reload; member
177 reg = readl(corediv->reg) | soc_desc->ratio_reload; in clk_corediv_set_rate()
185 reg &= ~(CORE_CLK_DIV_RATIO_MASK | soc_desc->ratio_reload); in clk_corediv_set_rate()
205 .ratio_reload = BIT(8),
221 .ratio_reload = BIT(8),
234 .ratio_reload = BIT(8),
246 .ratio_reload = BIT(10),

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