| /linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/ |
| A D | sdma_v2_4.c | 276 u32 ref_and_mask = 0; in sdma_v2_4_ring_emit_hdp_flush() local
279 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v2_4_ring_emit_hdp_flush()
281 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); in sdma_v2_4_ring_emit_hdp_flush()
288 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v2_4_ring_emit_hdp_flush()
289 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v2_4_ring_emit_hdp_flush()
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| A D | sdma_v3_0.c | 450 u32 ref_and_mask = 0; in sdma_v3_0_ring_emit_hdp_flush() local
453 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v3_0_ring_emit_hdp_flush()
455 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); in sdma_v3_0_ring_emit_hdp_flush()
462 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v3_0_ring_emit_hdp_flush()
463 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v3_0_ring_emit_hdp_flush()
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| A D | cik_sdma.c | 249 u32 ref_and_mask; in cik_sdma_ring_emit_hdp_flush() local
252 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK; in cik_sdma_ring_emit_hdp_flush()
254 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK; in cik_sdma_ring_emit_hdp_flush()
259 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_ring_emit_hdp_flush()
260 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_ring_emit_hdp_flush()
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| A D | sdma_v5_0.c | 486 u32 ref_and_mask = 0; in sdma_v5_0_ring_emit_hdp_flush() local
490 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; in sdma_v5_0_ring_emit_hdp_flush()
492 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; in sdma_v5_0_ring_emit_hdp_flush()
499 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v5_0_ring_emit_hdp_flush()
500 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v5_0_ring_emit_hdp_flush()
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| A D | sdma_v6_0.c | 307 u32 ref_and_mask = 0; in sdma_v6_0_ring_emit_hdp_flush() local
310 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v6_0_ring_emit_hdp_flush()
317 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v6_0_ring_emit_hdp_flush()
318 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v6_0_ring_emit_hdp_flush()
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| A D | sdma_v5_2.c | 292 u32 ref_and_mask = 0; in sdma_v5_2_ring_emit_hdp_flush() local
295 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v5_2_ring_emit_hdp_flush()
302 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v5_2_ring_emit_hdp_flush()
303 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v5_2_ring_emit_hdp_flush()
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| A D | sdma_v4_0.c | 814 u32 ref_and_mask = 0; in sdma_v4_0_ring_emit_hdp_flush() local
817 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v4_0_ring_emit_hdp_flush()
822 ref_and_mask, ref_and_mask, 10); in sdma_v4_0_ring_emit_hdp_flush()
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| A D | gfx_v7_0.c | 2065 u32 ref_and_mask; in gfx_v7_0_ring_emit_hdp_flush() local
2071 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; in gfx_v7_0_ring_emit_hdp_flush()
2074 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; in gfx_v7_0_ring_emit_hdp_flush()
2080 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; in gfx_v7_0_ring_emit_hdp_flush()
2089 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2090 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
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| A D | gfx_v8_0.c | 6043 u32 ref_and_mask, reg_mem_engine; in gfx_v8_0_ring_emit_hdp_flush() local
6049 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; in gfx_v8_0_ring_emit_hdp_flush()
6052 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; in gfx_v8_0_ring_emit_hdp_flush()
6059 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; in gfx_v8_0_ring_emit_hdp_flush()
6069 amdgpu_ring_write(ring, ref_and_mask); in gfx_v8_0_ring_emit_hdp_flush()
6070 amdgpu_ring_write(ring, ref_and_mask); in gfx_v8_0_ring_emit_hdp_flush()
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| A D | gfx_v9_0.c | 5073 u32 ref_and_mask, reg_mem_engine; in gfx_v9_0_ring_emit_hdp_flush() local
5079 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v9_0_ring_emit_hdp_flush()
5082 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v9_0_ring_emit_hdp_flush()
5089 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v9_0_ring_emit_hdp_flush()
5096 ref_and_mask, ref_and_mask, 0x20); in gfx_v9_0_ring_emit_hdp_flush()
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| A D | gfx_v11_0.c | 5338 u32 ref_and_mask, reg_mem_engine; in gfx_v11_0_ring_emit_hdp_flush() local
5344 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v11_0_ring_emit_hdp_flush()
5347 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v11_0_ring_emit_hdp_flush()
5354 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v11_0_ring_emit_hdp_flush()
5361 ref_and_mask, ref_and_mask, 0x20); in gfx_v11_0_ring_emit_hdp_flush()
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| A D | gfx_v10_0.c | 8374 u32 ref_and_mask, reg_mem_engine; in gfx_v10_0_ring_emit_hdp_flush() local
8380 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v10_0_ring_emit_hdp_flush()
8383 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v10_0_ring_emit_hdp_flush()
8390 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v10_0_ring_emit_hdp_flush()
8397 ref_and_mask, ref_and_mask, 0x20); in gfx_v10_0_ring_emit_hdp_flush()
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| /linux-6.3-rc2/drivers/gpu/drm/radeon/ |
| A D | cik_sdma.c | 174 u32 ref_and_mask; in cik_sdma_hdp_flush_ring_emit() local
177 ref_and_mask = SDMA0; in cik_sdma_hdp_flush_ring_emit()
179 ref_and_mask = SDMA1; in cik_sdma_hdp_flush_ring_emit()
184 radeon_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_hdp_flush_ring_emit()
185 radeon_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_hdp_flush_ring_emit()
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| A D | cik.c | 3498 u32 ref_and_mask; in cik_hdp_flush_cp_ring_emit() local
3506 ref_and_mask = CP2 << ring->pipe; in cik_hdp_flush_cp_ring_emit()
3509 ref_and_mask = CP6 << ring->pipe; in cik_hdp_flush_cp_ring_emit()
3516 ref_and_mask = CP0; in cik_hdp_flush_cp_ring_emit()
3526 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3527 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
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