Searched refs:regMP1_SMN_IH_SW_INT_CTRL (Results 1 – 6 of 6) sorted by relevance
| /linux-6.3-rc2/drivers/gpu/drm/amd/include/asic_reg/mp/ |
| A D | mp_13_0_8_offset.h | 382 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| A D | mp_13_0_2_offset.h | 387 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| A D | mp_13_0_4_offset.h | 380 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| A D | mp_13_0_0_offset.h | 379 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| A D | mp_13_0_5_offset.h | 381 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| /linux-6.3-rc2/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| A D | smu_v13_0.c | 1299 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v13_0_set_irq_state()
1301 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); in smu_v13_0_set_irq_state()
1332 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v13_0_set_irq_state()
1334 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); in smu_v13_0_set_irq_state()
1399 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v13_0_irq_process()
1401 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data); in smu_v13_0_irq_process()
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