Searched refs:reg_ctrl2 (Results 1 – 2 of 2) sorted by relevance
1233 u32 reg_fdcbt, reg_ctrl2; in flexcan_set_bittiming_cbt() local1269 reg_ctrl2 = priv->read(®s->ctrl2); in flexcan_set_bittiming_cbt()1275 priv->write(reg_ctrl2, ®s->ctrl2); in flexcan_set_bittiming_cbt()1338 u32 reg_ctrl2; in flexcan_ram_init() local1348 reg_ctrl2 = priv->read(®s->ctrl2); in flexcan_ram_init()1349 reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ; in flexcan_ram_init()1350 priv->write(reg_ctrl2, ®s->ctrl2); in flexcan_ram_init()1357 reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ; in flexcan_ram_init()1358 priv->write(reg_ctrl2, ®s->ctrl2); in flexcan_ram_init()1630 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE; in flexcan_chip_start()[all …]
847 u32 reg, reg_ctrl, reg_ctrl2; in dsi_update_dsc_timing() local885 reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); in dsi_update_dsc_timing()890 reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; in dsi_update_dsc_timing()891 reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size); in dsi_update_dsc_timing()894 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); in dsi_update_dsc_timing()
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