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Searched refs:reg_off (Results 1 – 25 of 59) sorted by relevance

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/linux-6.3-rc2/drivers/mmc/host/
A Dcavium.h37 #define MIO_EMM_CFG(x) (0x00 + x->reg_off)
38 #define MIO_EMM_SWITCH(x) (0x48 + x->reg_off)
39 #define MIO_EMM_DMA(x) (0x50 + x->reg_off)
40 #define MIO_EMM_CMD(x) (0x58 + x->reg_off)
42 #define MIO_EMM_RSP_LO(x) (0x68 + x->reg_off)
43 #define MIO_EMM_RSP_HI(x) (0x70 + x->reg_off)
44 #define MIO_EMM_INT(x) (0x78 + x->reg_off)
45 #define MIO_EMM_INT_EN(x) (0x80 + x->reg_off)
46 #define MIO_EMM_WDOG(x) (0x88 + x->reg_off)
49 #define MIO_EMM_RCA(x) (0xa0 + x->reg_off)
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/linux-6.3-rc2/drivers/pinctrl/sunplus/
A Dsppctl.c264 u32 reg_off, bit_off, reg; in sppctl_first_get() local
299 u32 reg_off, bit_off, reg; in sppctl_master_get() local
310 u32 reg_off, bit_off, reg; in sppctl_first_master_set() local
346 u32 reg_off, reg; in sppctl_gpio_input_inv_set() local
355 u32 reg_off, reg; in sppctl_gpio_output_inv_set() local
364 u32 reg_off, bit_off, reg; in sppctl_gpio_output_od_get() local
376 u32 reg_off, reg; in sppctl_gpio_output_od_set() local
417 u32 reg_off, reg; in sppctl_gpio_direction_input() local
433 u32 reg_off, reg; in sppctl_gpio_direction_output() local
467 u32 reg_off, reg; in sppctl_gpio_set() local
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/linux-6.3-rc2/tools/lib/bpf/
A Dusdt.c208 short reg_off; member
1197 #undef reg_off in calc_pt_regs_off()
1233 if (reg_off < 0) in parse_usdt_arg()
1235 arg->reg_off = reg_off; in parse_usdt_arg()
1243 arg->reg_off = reg_off; in parse_usdt_arg()
1252 arg->reg_off = reg_off; in parse_usdt_arg()
1364 arg->reg_off = reg_off; in parse_usdt_arg()
1372 arg->reg_off = reg_off; in parse_usdt_arg()
1385 arg->reg_off = reg_off; in parse_usdt_arg()
1472 arg->reg_off = reg_off; in parse_usdt_arg()
[all …]
A Dusdt.bpf.h45 short reg_off; member
153 err = bpf_probe_read_kernel(&val, sizeof(val), (void *)ctx + arg_spec->reg_off); in bpf_usdt_arg()
165 err = bpf_probe_read_kernel(&val, sizeof(val), (void *)ctx + arg_spec->reg_off); in bpf_usdt_arg()
/linux-6.3-rc2/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_vbif.c59 u32 reg_off; in dpu_hw_set_mem_type() local
79 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_mem_type()
82 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type()
90 u32 reg_off; in dpu_hw_set_limit_conf() local
94 reg_off = VBIF_IN_RD_LIM_CONF0; in dpu_hw_set_limit_conf()
96 reg_off = VBIF_IN_WR_LIM_CONF0; in dpu_hw_set_limit_conf()
98 reg_off += (xin_id / 4) * 4; in dpu_hw_set_limit_conf()
111 u32 reg_off; in dpu_hw_get_limit_conf() local
116 reg_off = VBIF_IN_RD_LIM_CONF0; in dpu_hw_get_limit_conf()
118 reg_off = VBIF_IN_WR_LIM_CONF0; in dpu_hw_get_limit_conf()
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A Ddpu_hw_catalog.c542 .reg_off = 0x2AC, .bit_off = 0},
544 .reg_off = 0x2AC, .bit_off = 8},
546 .reg_off = 0x2B4, .bit_off = 8},
548 .reg_off = 0x2C4, .bit_off = 8},
587 .reg_off = 0x2ac, .bit_off = 0},
589 .reg_off = 0x2ac, .bit_off = 8},
685 .reg_off = 0x2AC, .bit_off = 0},
687 .reg_off = 0x2AC, .bit_off = 8},
689 .reg_off = 0x2B4, .bit_off = 8},
691 .reg_off = 0x2C4, .bit_off = 8},
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A Ddpu_hw_top.c70 u32 reg_off, bit_off; in dpu_hw_setup_clk_force_ctrl() local
82 reg_off = mdp->caps->clk_ctrls[clk_ctrl].reg_off; in dpu_hw_setup_clk_force_ctrl()
85 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_setup_clk_force_ctrl()
92 DPU_REG_WRITE(c, reg_off, new_val); in dpu_hw_setup_clk_force_ctrl()
/linux-6.3-rc2/drivers/pinctrl/
A Dpinctrl-digicolor.c130 int bit_off, reg_off; in dc_set_mux() local
133 dc_client_sel(group, &reg_off, &bit_off); in dc_set_mux()
135 reg = readb_relaxed(pmap->regs + reg_off); in dc_set_mux()
138 writeb_relaxed(reg, pmap->regs + reg_off); in dc_set_mux()
148 int bit_off, reg_off; in dc_pmx_request_gpio() local
151 dc_client_sel(offset, &reg_off, &bit_off); in dc_pmx_request_gpio()
153 reg = readb_relaxed(pmap->regs + reg_off); in dc_pmx_request_gpio()
177 drive = readb_relaxed(pmap->regs + reg_off); in dc_gpio_direction_input()
179 writeb_relaxed(drive, pmap->regs + reg_off); in dc_gpio_direction_input()
199 drive = readb_relaxed(pmap->regs + reg_off); in dc_gpio_direction_output()
[all …]
/linux-6.3-rc2/drivers/clk/meson/
A Daxg.c29 .reg_off = HHI_MPLL_CNTL,
34 .reg_off = HHI_MPLL_CNTL,
39 .reg_off = HHI_MPLL_CNTL,
44 .reg_off = HHI_MPLL_CNTL2,
49 .reg_off = HHI_MPLL_CNTL,
54 .reg_off = HHI_MPLL_CNTL,
93 .reg_off = HHI_SYS_PLL_CNTL,
98 .reg_off = HHI_SYS_PLL_CNTL,
103 .reg_off = HHI_SYS_PLL_CNTL,
108 .reg_off = HHI_SYS_PLL_CNTL,
[all …]
A Dmeson8-ddr.c28 .reg_off = AM_DDR_PLL_CNTL,
33 .reg_off = AM_DDR_PLL_CNTL,
38 .reg_off = AM_DDR_PLL_CNTL,
43 .reg_off = AM_DDR_PLL_CNTL,
48 .reg_off = AM_DDR_PLL_CNTL,
A Dg12a-aoclk.c122 .reg_off = AO_RTC_ALT_CLK_CNTL0,
127 .reg_off = AO_RTC_ALT_CLK_CNTL0,
132 .reg_off = AO_RTC_ALT_CLK_CNTL1,
137 .reg_off = AO_RTC_ALT_CLK_CNTL1,
142 .reg_off = AO_RTC_ALT_CLK_CNTL0,
213 .reg_off = AO_CEC_CLK_CNTL_REG0,
218 .reg_off = AO_CEC_CLK_CNTL_REG0,
223 .reg_off = AO_CEC_CLK_CNTL_REG1,
228 .reg_off = AO_CEC_CLK_CNTL_REG1,
233 .reg_off = AO_CEC_CLK_CNTL_REG0,
A Dgxbb.c89 .reg_off = HHI_MPLL_CNTL,
94 .reg_off = HHI_MPLL_CNTL,
99 .reg_off = HHI_MPLL_CNTL,
104 .reg_off = HHI_MPLL_CNTL2,
109 .reg_off = HHI_MPLL_CNTL,
114 .reg_off = HHI_MPLL_CNTL,
718 .reg_off = HHI_MPLL_CNTL7,
723 .reg_off = HHI_MPLL_CNTL,
728 .reg_off = HHI_MPLL_CNTL7,
747 .reg_off = HHI_MPLL_CNTL7,
[all …]
A Dparm.h25 u16 reg_off; member
34 regmap_read(map, p->reg_off, &val); in meson_parm_read()
41 regmap_update_bits(map, p->reg_off, SETPMASK(p->width, p->shift), in meson_parm_write()
A Dgxbb-aoclk.c89 .reg_off = AO_RTC_ALT_CLK_CNTL0,
94 .reg_off = AO_RTC_ALT_CLK_CNTL0,
99 .reg_off = AO_RTC_ALT_CLK_CNTL1,
104 .reg_off = AO_RTC_ALT_CLK_CNTL1,
109 .reg_off = AO_RTC_ALT_CLK_CNTL0,
A Dg12a.c33 .reg_off = HHI_FIX_PLL_CNTL0,
38 .reg_off = HHI_FIX_PLL_CNTL0,
43 .reg_off = HHI_FIX_PLL_CNTL0,
48 .reg_off = HHI_FIX_PLL_CNTL1,
53 .reg_off = HHI_FIX_PLL_CNTL0,
58 .reg_off = HHI_FIX_PLL_CNTL0,
102 .reg_off = HHI_SYS_PLL_CNTL0,
107 .reg_off = HHI_SYS_PLL_CNTL0,
112 .reg_off = HHI_SYS_PLL_CNTL0,
117 .reg_off = HHI_SYS_PLL_CNTL0,
[all …]
A Daxg-aoclk.c103 .reg_off = AO_RTC_ALT_CLK_CNTL0,
108 .reg_off = AO_RTC_ALT_CLK_CNTL0,
113 .reg_off = AO_RTC_ALT_CLK_CNTL1,
118 .reg_off = AO_RTC_ALT_CLK_CNTL1,
123 .reg_off = AO_RTC_ALT_CLK_CNTL0,
A Dmeson8b.c58 .reg_off = HHI_MPLL_CNTL,
63 .reg_off = HHI_MPLL_CNTL,
68 .reg_off = HHI_MPLL_CNTL,
73 .reg_off = HHI_MPLL_CNTL2,
78 .reg_off = HHI_MPLL_CNTL,
83 .reg_off = HHI_MPLL_CNTL,
472 .reg_off = HHI_MPLL_CNTL7,
477 .reg_off = HHI_MPLL_CNTL7,
482 .reg_off = HHI_MPLL_CNTL7,
487 .reg_off = HHI_MPLL_CNTL,
[all …]
/linux-6.3-rc2/sound/soc/tegra/
A Dtegra210_mbdrc.c852 reg_off + TEGRA210_MBDRC_IIR_CFG, in tegra210_mbdrc_component_init()
858 reg_off + TEGRA210_MBDRC_IN_ATTACK, in tegra210_mbdrc_component_init()
864 reg_off + TEGRA210_MBDRC_IN_RELEASE, in tegra210_mbdrc_component_init()
870 reg_off + TEGRA210_MBDRC_FAST_ATTACK, in tegra210_mbdrc_component_init()
910 reg_off + TEGRA210_MBDRC_RATIO_1ST, in tegra210_mbdrc_component_init()
915 reg_off + TEGRA210_MBDRC_RATIO_2ND, in tegra210_mbdrc_component_init()
920 reg_off + TEGRA210_MBDRC_RATIO_3RD, in tegra210_mbdrc_component_init()
925 reg_off + TEGRA210_MBDRC_RATIO_4TH, in tegra210_mbdrc_component_init()
930 reg_off + TEGRA210_MBDRC_RATIO_5TH, in tegra210_mbdrc_component_init()
935 reg_off + TEGRA210_MBDRC_MAKEUP_GAIN, in tegra210_mbdrc_component_init()
[all …]
/linux-6.3-rc2/drivers/net/ethernet/marvell/octeon_ep/
A Doctep_main.h289 #define octep_write_csr(octep_dev, reg_off, value) \ argument
290 writel(value, (octep_dev)->mmio[0].hw_addr + (reg_off))
292 #define octep_write_csr64(octep_dev, reg_off, val64) \ argument
293 writeq(val64, (octep_dev)->mmio[0].hw_addr + (reg_off))
295 #define octep_read_csr(octep_dev, reg_off) \ argument
296 readl((octep_dev)->mmio[0].hw_addr + (reg_off))
298 #define octep_read_csr64(octep_dev, reg_off) \ argument
299 readq((octep_dev)->mmio[0].hw_addr + (reg_off))
/linux-6.3-rc2/drivers/thermal/samsung/
A Dexynos_tmu.c442 unsigned int reg_off, j; in exynos5433_tmu_set_trip_temp() local
446 reg_off = EXYNOS5433_THD_TEMP_RISE7_4; in exynos5433_tmu_set_trip_temp()
453 th = readl(data->base + reg_off); in exynos5433_tmu_set_trip_temp()
456 writel(th, data->base + reg_off); in exynos5433_tmu_set_trip_temp()
462 unsigned int reg_off, j; in exynos5433_tmu_set_trip_hyst() local
473 th = readl(data->base + reg_off); in exynos5433_tmu_set_trip_hyst()
476 writel(th, data->base + reg_off); in exynos5433_tmu_set_trip_hyst()
515 unsigned int reg_off, bit_off; in exynos7_tmu_set_trip_temp() local
518 reg_off = ((7 - trip) / 2) * 4; in exynos7_tmu_set_trip_temp()
530 unsigned int reg_off, bit_off; in exynos7_tmu_set_trip_hyst() local
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/linux-6.3-rc2/drivers/net/ethernet/cavium/liquidio/
A Docteon_device.h740 #define octeon_write_csr(oct_dev, reg_off, value) \ argument
741 writel(value, (oct_dev)->mmio[0].hw_addr + (reg_off))
743 #define octeon_write_csr64(oct_dev, reg_off, val64) \ argument
744 writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off))
746 #define octeon_read_csr(oct_dev, reg_off) \ argument
747 readl((oct_dev)->mmio[0].hw_addr + (reg_off))
749 #define octeon_read_csr64(oct_dev, reg_off) \ argument
750 readq((oct_dev)->mmio[0].hw_addr + (reg_off))
/linux-6.3-rc2/drivers/pinctrl/spear/
A Dpinctrl-plgpio.c85 u32 reg_off = REG_OFFSET(0, reg, pin); in is_plgpio_set() local
88 regmap_read(regmap, reg_off, &val); in is_plgpio_set()
96 u32 reg_off = REG_OFFSET(0, reg, pin); in plgpio_reg_set() local
100 regmap_update_bits(regmap, reg_off, mask, mask); in plgpio_reg_set()
106 u32 reg_off = REG_OFFSET(0, reg, pin); in plgpio_reg_reset() local
110 regmap_update_bits(regmap, reg_off, mask, 0); in plgpio_reg_reset()
330 u32 reg_off; in plgpio_irq_set_type() local
347 reg_off = REG_OFFSET(0, plgpio->regs.eit, offset); in plgpio_irq_set_type()
348 regmap_read(plgpio->regmap, reg_off, &val); in plgpio_irq_set_type()
352 regmap_write(plgpio->regmap, reg_off, val | (1 << offset)); in plgpio_irq_set_type()
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/linux-6.3-rc2/drivers/accel/habanalabs/goya/
A Dgoya.c1103 WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0); in goya_init_dma_qman()
1104 WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0); in goya_init_dma_qman()
1112 WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off, in goya_init_dma_qman()
1116 WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002); in goya_init_dma_qman()
1117 WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008); in goya_init_dma_qman()
1144 WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off, in goya_init_dma_ch()
1952 WREG32(mmTPC0_QM_PQ_PI + reg_off, 0); in goya_init_tpc_qman()
1953 WREG32(mmTPC0_QM_PQ_CI + reg_off, 0); in goya_init_tpc_qman()
1964 WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008); in goya_init_tpc_qman()
1969 WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off, in goya_init_tpc_qman()
[all …]
/linux-6.3-rc2/arch/x86/kvm/
A Dlapic.h174 static inline u32 __kvm_lapic_get_reg(char *regs, int reg_off) in __kvm_lapic_get_reg() argument
176 return *((u32 *) (regs + reg_off)); in __kvm_lapic_get_reg()
179 static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) in kvm_lapic_get_reg() argument
181 return __kvm_lapic_get_reg(apic->regs, reg_off); in kvm_lapic_get_reg()
/linux-6.3-rc2/drivers/mtd/nand/raw/
A Dqcom_nandc.c910 int reg_off, const void *vaddr, in prep_bam_dma_desc_cmd() argument
924 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd()
930 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd()
1735 int ret, reg_off = FLASH_BUF_ACC, read_loc = 0; in qcom_nandc_read_cw_raw() local
1778 reg_off += data_size1; in qcom_nandc_read_cw_raw()
1781 reg_off += oob_size1; in qcom_nandc_read_cw_raw()
1784 reg_off += data_size2; in qcom_nandc_read_cw_raw()
2318 int reg_off = FLASH_BUF_ACC; in qcom_nandc_write_page_raw() local
2335 reg_off += data_size1; in qcom_nandc_write_page_raw()
2340 reg_off += oob_size1; in qcom_nandc_write_page_raw()
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