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Searched refs:reo_base (Results 1 – 3 of 3) sorted by relevance

/linux-6.3-rc2/drivers/net/wireless/ath/ath11k/
A Dhw.c107 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; in ath11k_hw_ipq8074_reo_setup() local
119 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); in ath11k_hw_ipq8074_reo_setup()
126 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); in ath11k_hw_ipq8074_reo_setup()
137 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0, in ath11k_hw_ipq8074_reo_setup()
140 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1, in ath11k_hw_ipq8074_reo_setup()
143 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, in ath11k_hw_ipq8074_reo_setup()
146 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, in ath11k_hw_ipq8074_reo_setup()
757 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; in ath11k_hw_wcn6855_reo_setup() local
769 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); in ath11k_hw_wcn6855_reo_setup()
772 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); in ath11k_hw_wcn6855_reo_setup()
[all …]
/linux-6.3-rc2/drivers/net/wireless/ath/ath12k/
A Dhal_rx.c818 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; in ath12k_hal_reo_hw_setup() local
821 val = ath12k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); in ath12k_hal_reo_hw_setup()
825 ath12k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); in ath12k_hal_reo_hw_setup()
827 val = ath12k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTRL_ADDR(ab)); in ath12k_hal_reo_hw_setup()
835 ath12k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTRL_ADDR(ab), val); in ath12k_hal_reo_hw_setup()
837 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), in ath12k_hal_reo_hw_setup()
839 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), in ath12k_hal_reo_hw_setup()
841 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), in ath12k_hal_reo_hw_setup()
843 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), in ath12k_hal_reo_hw_setup()
846 ath12k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, in ath12k_hal_reo_hw_setup()
[all …]
A Ddp.c1229 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; in ath12k_dp_cc_config() local
1233 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG0(ab), cmem_base); in ath12k_dp_cc_config()
1245 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG1(ab), val); in ath12k_dp_cc_config()

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