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/linux-6.3-rc2/drivers/accel/habanalabs/include/gaudi2/
A Dgaudi2_async_ids_map_extended.h21 int reset; member
27 .msg = 0, .reset = 0, .name = "" },
29 .msg = 0, .reset = 0, .name = "" },
31 .msg = 0, .reset = 0, .name = "" },
33 .msg = 0, .reset = 0, .name = "" },
35 .msg = 0, .reset = 0, .name = "" },
37 .msg = 0, .reset = 0, .name = "" },
39 .msg = 0, .reset = 0, .name = "" },
41 .msg = 0, .reset = 0, .name = "" },
43 .msg = 0, .reset = 0, .name = "" },
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/linux-6.3-rc2/Documentation/devicetree/bindings/reset/
A Dzynq-reset.txt25 0 : soft reset
26 32 : ddr reset
28 96 : dmac reset
29 128: usb0 reset
30 129: usb1 reset
31 160: gem0 reset
32 161: gem1 reset
41 224: spi0 reset
42 225: spi1 reset
58 416: smc reset
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A Dsocionext,uniphier-reset.yaml4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-reset.yaml#
7 title: UniPhier reset controller
15 - description: System reset
17 - socionext,uniphier-ld4-reset
18 - socionext,uniphier-pro4-reset
27 - description: Media I/O (MIO) reset, SD reset
39 - description: Peripheral reset
55 "#reset-cells":
65 - "#reset-cells"
69 reset-controller {
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A Dreset.txt10 reset consumer (the module being reset, or a module managing when a sub-
14 A reset signal is represented by the phandle of the provider, plus a reset
24 may be reset. Instead, reset signals should be represented in the DT node
35 #reset-cells: Number of cells in a reset specifier; Typically 0 for nodes
37 reset outputs.
41 rst: reset-controller {
42 #reset-cells = <1>;
55 reset-names: List of reset signal name strings sorted in the same order as
57 match reset signal names with reset specifiers.
63 reset-names = "reset";
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A Dsocionext,uniphier-glue-reset.yaml4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#
26 - socionext,uniphier-nx1-usb3-reset
34 "#reset-cells":
47 reset-names: true
70 reset-names:
82 reset-names:
90 - "#reset-cells"
94 - reset-names
98 usb_rst: reset-controller@0 {
101 #reset-cells = <1>;
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A Dti-syscon-reset.txt27 "ti,syscon-reset"
28 - #reset-cells : Should be 1. Please see the reset consumer node below
30 - ti,reset-bits : Contains the reset control register information
35 Cell #2 : bit position of the reset in the reset
39 Cell #4 : bit position of the reset in the reset
44 reset status register
57 to a reset specifier as defined above.
59 Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
74 pscrst: reset-controller {
76 #reset-cells = <1>;
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A Dsnps,hsdk-reset.txt1 Binding for the Synopsys HSDK reset controller
3 This binding uses the common reset binding[1].
5 [1] Documentation/devicetree/bindings/reset/reset.txt
8 - compatible: should be "snps,hsdk-reset".
12 - #reset-cells: from common reset binding; Should always be set to 1.
15 reset: reset@880 {
16 compatible = "snps,hsdk-reset";
17 #reset-cells = <1>;
21 Specifying reset lines connected to IP modules:
24 resets = <&reset HSDK_V1_ETH_RESET>;
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A Dxlnx,zynqmp-reset.txt9 Please also refer to reset.txt in this directory for common reset
14 "xlnx,versal-reset" for Versal platform
15 - #reset-cells: Specifies the number of cells needed to encode reset
27 zynqmp_reset: reset-controller {
28 compatible = "xlnx,zynqmp-reset";
29 #reset-cells = <1>;
34 Specifying reset lines connected to IP modules
39 specified in reset.txt.
42 <dt-bindings/reset/xlnx-zynqmp-resets.h>
44 <dt-bindings/reset/xlnx-versal-resets.h>
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A Dbrcm,brcmstb-reset.yaml4 $id: "http://devicetree.org/schemas/reset/brcm,brcmstb-reset.yaml#"
12 reset lines.
14 Please also refer to reset.txt in this directory for common reset
22 const: brcm,brcmstb-reset
27 "#reset-cells":
33 - "#reset-cells"
39 reset: reset-controller@8404318 {
40 compatible = "brcm,brcmstb-reset";
42 #reset-cells = <1>;
46 resets = <&reset 26>;
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A Dimg,pistachio-reset.txt13 Please refer to Documentation/devicetree/bindings/reset/reset.txt
14 for common reset controller binding usage.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
33 #reset-cells = <1>;
37 Specifying reset control of devices
43 Documentation/devicetree/bindings/reset/reset.txt.
50 reset-names = "rst";
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A Dfsl,imx7-src.yaml4 $id: http://devicetree.org/schemas/reset/fsl,imx7-src.yaml#
13 The system reset controller can be used to reset various set of
16 specified in reset.txt.
18 For list of all valid reset indices see
19 <dt-bindings/reset/imx7-reset.h> for i.MX7,
20 <dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ, i.MX8MM and i.MX8MN,
21 <dt-bindings/reset/imx8mp-reset.h> for i.MX8MP.
45 '#reset-cells':
52 - '#reset-cells'
60 reset-controller@30390000 {
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A Dallwinner,sun6i-a31-clock-reset.yaml4 $id: http://devicetree.org/schemas/reset/allwinner,sun6i-a31-clock-reset.yaml#
20 - allwinner,sun6i-a31-ahb1-reset
21 - allwinner,sun6i-a31-clock-reset
31 "#reset-cells":
40 - allwinner,sun6i-a31-ahb1-reset
41 - allwinner,sun6i-a31-clock-reset
47 - "#reset-cells"
55 ahb1_rst: reset@1c202c0 {
56 #reset-cells = <1>;
62 apbs_rst: reset@80014b0 {
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A Dnuvoton,npcm750-reset.yaml4 $id: http://devicetree.org/schemas/reset/nuvoton,npcm750-reset.yaml#
15 - nuvoton,npcm750-reset # Poleg NPCM7XX SoC
16 - nuvoton,npcm845-reset # Arbel NPCM8XX SoC
21 '#reset-cells':
28 nuvoton,sw-reset-number:
34 If not specified, software reset is disabled.
39 - '#reset-cells'
46 #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
48 compatible = "nuvoton,npcm750-reset";
50 #reset-cells = <2>;
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A Dsnps,axs10x-reset.yaml4 $id: http://devicetree.org/schemas/reset/snps,axs10x-reset.yaml#
7 title: AXS10x reset controller
16 represents up-to 32 reset lines.
22 const: snps,axs10x-reset
27 '#reset-cells':
33 - '#reset-cells'
39 reset: reset-controller@11220 {
40 compatible = "snps,axs10x-reset";
41 #reset-cells = <1>;
45 // Specifying reset lines connected to IP modules:
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A Dqca,ar7100-reset.yaml5 $id: "http://devicetree.org/schemas/reset/qca,ar7100-reset.yaml#"
8 title: Qualcomm Atheros AR7xxx/AR9XXX reset controller
17 - qca,ar9132-reset
18 - qca,ar9331-reset
19 - const: qca,ar7100-reset
24 "#reset-cells":
30 - "#reset-cells"
36 reset-controller@1806001c {
37 compatible = "qca,ar9132-reset", "qca,ar7100-reset";
39 #reset-cells = <1>;
A Dhisilicon,hi3660-reset.yaml4 $id: http://devicetree.org/schemas/reset/hisilicon,hi3660-reset.yaml#
13 Please also refer to reset.txt in this directory for common reset
22 - const: hisilicon,hi3660-reset
24 - const: hisilicon,hi3670-reset
25 - const: hisilicon,hi3660-reset
33 description: phandle of the reset's syscon.
36 '#reset-cells':
43 Cell #2 : bit position of the reset in the reset control register
63 compatible = "hisilicon,hi3660-reset";
65 #reset-cells = <2>;
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/linux-6.3-rc2/drivers/reset/
A DMakefile6 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
7 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
8 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
10 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
13 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
14 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
16 obj-$(CONFIG_RESET_K210) += reset-k210.o
20 obj-$(CONFIG_RESET_MESON) += reset-meson.o
22 obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
30 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
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A Dreset-sunplus.c162 sp_reset_assert(&reset->rcdev, 0); in sp_restart()
163 sp_reset_deassert(&reset->rcdev, 0); in sp_restart()
171 struct sp_reset *reset; in sp_reset_probe() local
175 reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL); in sp_reset_probe()
176 if (!reset) in sp_reset_probe()
181 if (IS_ERR(reset->base)) in sp_reset_probe()
182 return PTR_ERR(reset->base); in sp_reset_probe()
184 reset->rcdev.ops = &sp_reset_ops; in sp_reset_probe()
185 reset->rcdev.owner = THIS_MODULE; in sp_reset_probe()
186 reset->rcdev.of_node = dev->of_node; in sp_reset_probe()
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A DKconfig30 AR71xx SoC reset controller.
53 tristate "Broadcom STB reset controller"
92 Say Y to control the reset signals provided by reset controller.
118 bool "Microchip Sparx5 reset driver"
189 initialization routines as reset lines.
214 This enables a simple reset controller driver for reset lines that
223 - RCC reset controller in STM32 MCUs
295 called reset-tn48m.
323 source "drivers/reset/sti/Kconfig"
324 source "drivers/reset/hisilicon/Kconfig"
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/linux-6.3-rc2/drivers/power/reset/
A Dat91-reset.c140 : "r" (reset->ramc_base[0]), in at91_reset()
141 "r" (reset->ramc_base[1]), in at91_reset()
142 "r" (reset->rstc_base), in at91_reset()
146 "r" (reset->ramc_lpr) in at91_reset()
323 reset->rcdev.nr_resets = reset->data->n_device_reset; in at91_rcdev_init()
333 struct at91_reset *reset; in at91_reset_probe() local
337 reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); in at91_reset_probe()
338 if (!reset) in at91_reset_probe()
362 if (!reset->data) in at91_reset_probe()
366 reset->nb.priority = 192; in at91_reset_probe()
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/linux-6.3-rc2/Documentation/driver-api/
A Dreset.rst15 over their reset input signals, and the `reset controller driver interface
17 <#reset-controller-driver-api>`__), which is used by drivers for reset
31 Physical reset line carrying a reset signal from a reset controller
40 reset line.
52 reset line.
61 trigger reset pulses, or to query reset line status.
64 reset inputs, which are mapped to an actual reset control on an existing reset
127 Only some reset controllers support querying the current status of a reset
130 reset line is asserted.
159 assert or deassert reset signals, to trigger a reset pulse on a reset line, or
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/linux-6.3-rc2/drivers/clk/visconti/
A Dreset.c31 spin_lock_irqsave(reset->lock, flags); in visconti_reset_assert()
82 .reset = visconti_reset_reset,
93 struct visconti_reset *reset; in visconti_register_reset_controller() local
95 reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL); in visconti_register_reset_controller()
96 if (!reset) in visconti_register_reset_controller()
99 reset->regmap = regmap; in visconti_register_reset_controller()
100 reset->resets = resets; in visconti_register_reset_controller()
101 reset->rcdev.ops = reset_ops; in visconti_register_reset_controller()
102 reset->rcdev.nr_resets = num_resets; in visconti_register_reset_controller()
103 reset->rcdev.of_node = dev->of_node; in visconti_register_reset_controller()
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/linux-6.3-rc2/Documentation/devicetree/bindings/power/reset/
A Dkeystone-reset.txt3 This node is intended to allow SoC reset in case of software reset
14 - compatible: ti,keystone-reset
18 reset control registers.
26 - ti,soft-reset: Boolean option indicating soft reset.
27 By default hard reset is used.
37 Setup keystone reset so that in case software reset or
50 rstctrl: reset-controller {
51 compatible = "ti,keystone-reset";
58 Setup keystone reset so that in case of software reset or
61 rstctrl: reset-controller {
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/linux-6.3-rc2/arch/arm64/boot/dts/apple/
A Dt8103-pmgr.dtsi14 #reset-cells = <0>;
23 #reset-cells = <0>;
32 #reset-cells = <0>;
41 #reset-cells = <0>;
49 #reset-cells = <0>;
57 #reset-cells = <0>;
65 #reset-cells = <0>;
73 #reset-cells = <0>;
82 #reset-cells = <0>;
91 #reset-cells = <0>;
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/linux-6.3-rc2/drivers/soc/ti/
A Domap_prm.c760 v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); in omap_reset_status()
768 v = readl_relaxed(reset->prm->base + reset->prm->data->rstst); in omap_reset_status()
784 v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); in omap_reset_assert()
786 writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); in omap_reset_assert()
815 writel_relaxed(v, reset->prm->base + reset->prm->data->rstst); in omap_reset_deassert()
823 v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); in omap_reset_deassert()
825 writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); in omap_reset_deassert()
897 reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); in omap_prm_reset_init()
898 if (!reset) in omap_prm_reset_init()
929 if ((v & reset->mask) != reset->mask) { in omap_prm_reset_init()
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